A43E06161V AMICC [AMIC Technology], A43E06161V Datasheet - Page 10

• Manufacturer Part Number: A43E06161V
• Description: 512K X 16 Bit X 2 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Mode Register Filed Table to Program Modes
Register Programmed with MRS
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 µ s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
PRELIMINARY
A9
A8
Address
0
1
Function
0
0
1
1
A7
Write Burst Length
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
0
1
0
1
(Note 1)
Test Mode
Mode Register Set
RFU
Single Bit
BA
Length
Burst
(July, 2005, Version 0.1)
Vendor
Type
(Note 2)
Only
Use
A10/AP
RFU
W.B.L
A9
A6
0
0
0
0
1
1
1
1
A5
0
1
1
0
1
1
0
0
CAS Latency
A8
A4
0
1
0
1
0
1
0
1
TM
Reserved
Reserved
Reserved
Reserved
Reserved
A7
Latency
2
3
-
9
A6
A3
0
1
CAS Latency
Burst Type
Sequential
A5
Interleave
Type
A4
A2
0
0
0
0
1
1
1
1
A1
A3
BT
0
0
1
1
0
0
1
1
AMIC Technology, Corp.
A0
0
1
0
1
0
1
0
1
Burst Length
A2
Reserved
Reserved
Reserved
256(Full)
BT=0
1
2
4
8
Burst Length
A43E06161
A1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BT=1
(Note 3)
4
8
A0