A43E06161V AMICC [AMIC Technology], A43E06161V Datasheet - Page 35

• Manufacturer Part Number: A43E06161V
• Description: 512K X 16 Bit X 2 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

CLOCK
A10/AP
Burst Read Single Bit Write Cycle @Burst Length=2, BRSW
PRELIMINARY
ADDR
RAS
CAS
(CL=2)
(CL=3)
CKE
DQM
BA
CS
DQ
DQ
WE
0
Row Active
* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
(A-Bank)
RAa
RAa
1
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
(July, 2005, Version 0.1)
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
The next cycle starts the precharge.
2
3
(A-Bank)
Write
DAa0
DAa0
CAa
4
Row Active
(B-Bank)
RBb
RBb
Auto Precharge
5
Read with
(A-Bank)
CAb
6
7
QAb0
8
QAb0
QAb1
34
9
High
QAb1
10
Row Active
(A-Bank)
RAc
RAc
Auto Precharge
11
Write with
(B-Bank)
DBc0
DBc0
CBc
12
* Note 2
13
(A-Bank)
Read
CAd
14
AMIC Technology, Corp.
15
QAd0
16
QAd1
QAd0
A43E06161
17
Precharge
(A-Bank)
QAd1
: Don't care
18
19