A43E06161V AMICC [AMIC Technology], A43E06161V Datasheet - Page 31

• Manufacturer Part Number: A43E06161V
• Description: 512K X 16 Bit X 2 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

CLOCK
PRELIMINARY
Read & Write Cycle with Auto Precharge II @Burst Length=4
A10/AP
ADDR
(CL=2)
(CL=3)
RAS
CAS
CKE
DQM
CS
DQ
DQ
WE
BA
0
Row Active
* Note :
(A-Bank)
Ra
Ra
1
(July, 2005, Version 0.1)
- Any command can not be issued at A Bank during t
- if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto
When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
2
precharge will start at B Bank read command input point.
3
Row Active
(B-Bank)
Rb
Rb
4
Read with
(A-Bank)
Auto Pre
Charge
Ca
5
Auto Precharge
Auto Precharge
(A-Bank)
6
Read without
Strart Point
(B-Bank)
Qa0
Cb
7
*Note 1
Qa0
Qa1
8
Qa1
Qb0
9
High
30
Qb1
Qb0
RP
10
after A Bank auto precharge starts.
Qb2
Qb1
11
Precharge
(B-Bank)
Qb3
Qb2
12
Qb3
13
14
Row Active
(A-Bank)
Ra
Ra
AMIC Technology, Corp.
15
16
17
A43E06161
: Don't care
Auto Precharge
18
Write with
(A-Bank)
Da0
Da0
Ca
19
Da1
Da1