em78f644nso28s ELAN Microelectronics Corp, em78f644nso28s Datasheet - Page 109

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em78f644nso28s

Manufacturer Part Number
em78f644nso28s
Description
Flash Series 8-bit Microcontroller
Manufacturer
ELAN Microelectronics Corp
Datasheet
Product Specification (V1.0) 05.05.2010
(This specification is subject to change without further notice)
6.6.3
During Receiving, the UART operates as follows:
1. Sets RXE bit of the URS register to enable the UART receiving function. The
2. Received data is shifted into the URRD register in LSB to MSB order.
3. The parity bit and the stop bit are received. After one character is received, the
4. The UART then makes the following checks:
5. Read the received data from URRD register and the URBF bit will be cleared by
6.6.4 Baud Rate Generator
The baud rate generator features a circuit that generates a clock pulse to determine
the transfer speed for transmission/reception in the UART.
The BRATE2~BRATE0 bits of the URC register determine the desired baud rate.
6.6.5 UART Timing
Transmission Counter Timing:
UART monitors the RX pin and synchronizes internally when it detects a Start bit.
URBF bit of the URS register will be set to “1” to allow UART interrupt to occur.
If any of the checks failed, the UERRIF interrupt will be generated (if enabled),
and an error flag is indicated in PRERR, OVERR or FMERR bit. The error flag
should be cleared by software. Otherwise, UERRIF interrupt will occur when the
next byte is received.
hardware.
a) Parity check:
b) Frame check:
c) Overrun check: The URBF bit of the URS register must be cleared (i.e., the
Figure 6-14a UART Transmission Counter Timing Diagram
Receiving
The number of ones (“1”) of the received data must match
the even or odd parity setting of the EVEN bit in the URS
register.
The start bit must be “0” and the stop bit must be “1”.
URRD register should be read out) before the next received
data is loaded into the URRD register.
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
• 99

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