em78f644nso28s ELAN Microelectronics Corp, em78f644nso28s Datasheet - Page 117

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em78f644nso28s

Manufacturer Part Number
em78f644nso28s
Description
Flash Series 8-bit Microcontroller
Manufacturer
ELAN Microelectronics Corp
Datasheet
Product Specification (V1.0) 05.05.2010
(This specification is subject to change without further notice)
The EM78F648N/F548N supports a bidirectional, 2-wire bus, 7-bits & 10-bits
addressing and data transmission protocol. A device that sends data onto the bus is
defined as transmitter, while a device that receives data is defined as a receiver. The
bus has to be controlled by a Master device which generates the Serial Clock (SCL),
controls the bus access, and generates the Start and Stop conditions. Both Master
and Slave can operate as transmitter or receiver, but only the Master device can
determine which mode is activated.
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via
a pull-up resistor. When the bus is free, both lines are HIGH. The output stages of
the devices that are connected to the bus must have an open-drain or open-collector
to perform the wired-AND function. Data on the I2C-bus can be transferred at the
rates of up to 100k bit/s in Standard-mode or up to 400k bit/s in the Fast-mode.
The data on the SDA line must be stable during the HIGH period of the clock. The
HIGH or LOW state of the data line can only change when the clock signal on the
SCL line is LOW.
Within the procedure of the I2C bus, unique situations could arise, which are defined
as START (S) and STOP (P) conditions.
A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique
case. This situation indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition.
Figure 6-18b I2C Transfer Condition
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
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