hm5216805 Renesas Electronics Corporation., hm5216805 Datasheet - Page 39

• Manufacturer Part Number: hm5216805
• Description: 16 M Lvttl Interface Sdram 100 Mhz/83 Mhz 1-mword 8-bit 2-bank/2-mword 4-bit 2-bank - Hitachi Semiconductor
• Manufacturer: Renesas Electronics Corporation.

HM5216805 Series, HM5216405 Series
Refresh
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the
auto-refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
4,096 cycles/64 ms. (4,096 cycles are required to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not
required.
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is
held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self-refresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with
15.6 s interval in normal read/write cycle, auto-refresh should be executed within 15.6 s immediately
after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-
refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 s interval
should be executed within 64 ms immediately after exiting from and before entering into self refresh mode.
Others
Power-down mode: The synchronous DRAM enters power-down mode when CKE goes Low in the IDLE
state. In power down mode, power consumption is suppressed by deactivating the input initial circuit.
Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the
synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle.
In this mode, internal refresh is not performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the
synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are
ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM
terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the
"CKE Truth Table".
Power-up sequence: During power-up sequence, the DQM and the CKE must be set to High. When 200
s has past after power on, all banks must be precharged using the precharge command. After t
delay, set
RP
8 or more auto refresh commands. And set the mode register set command to initialize the mode register.
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