hm5216805 Renesas Electronics Corporation., hm5216805 Datasheet - Page 9

• Manufacturer Part Number: hm5216805
• Description: 16 M Lvttl Interface Sdram 100 Mhz/83 Mhz 1-mword 8-bit 2-bank/2-mword 4-bit 2-bank - Hitachi Semiconductor
• Manufacturer: Renesas Electronics Corporation.

Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional
DRAMs, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY8; HM5216805 Series, AY0 to AY9;
HM5216405 Series) is determined by A0 to A8 or A9 (A8; HM5216805 Series, A9; HM5216405 Series)
level at the read or write command cycle CLK rising edge. And this column address becomes burst access
start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both
banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is
selected by A11(BS) is precharged.
A11 (input pin): A11 is a bank select signal (BS). The memory array of the HM5216805 Series, the
HM5216405 Series is divided into bank 0 and bank 1. HM5216805 Series contain 2048 row
and if A11 is High, bank 1 is selected.
CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next
CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-
down and clock suspend modes.
DQM (input pins): DQM controls input/output buffers.
Read operation: If DQM is High, the output buffer becomes High-Z. If the DQM is Low, the output buffer
becomes Low-Z.
Write operation: If DQM is High, the previous data is held (the new data is not written). If DQM is Low,
the data is written.
I/O0 to I/O7 (I/O pins): Data is input to and output from these pins. These pins are the same as those of a
conventional DRAM.
V
output buffer.)
V
the output buffer.)
CC
SS
8 bits. HM5216405 Series contain 2048 row
and V
and V
SS
CC
Q (power supply pins): Ground is connected. (V
Q (power supply pins): 3.3 V is applied. (V
HM5216805 Series, HM5216405 Series
1024 column
CC
is for the internal circuit and V
SS
is for the internal circuit and V
4 bits. If A11 is Low, bank 0 is selected,
CC
512 column
Q is for the
SS
Q is for
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