MK50H25DIP ST Microelectronics, Inc., MK50H25DIP Datasheet - Page 33

• Manufacturer Part Number: MK50H25DIP
• Description: High Speed Link Level Controller
• Manufacturer: ST Microelectronics, Inc.

4.2.5 Receive Descriptor Ring Pointer
4.2.6 Transmit Descriptor Ring Pointer
15
14:12
11
10
09
08
07:00/15:00
BIT
15
BIT
IADR + 18
IADR + 16
IADR + 20
IADR + 22
NAME
RINTD
RLEN
RBSY
RBFCS
FCSER
FCSEN
NAME
0
RDRA
1
5
R
I
N
T
D
1
5
0
1
4
DESCRIPTION
RECEIVE INTERRUPT DISABLE. Setting this bit will cause no Receive
Interrupt (RINT) to be generated upon the reception of any frame.
RECEIVE RING LENGTH is the number of entries in the Receive
Ring expressed as a power of two.
Remote Busy indication enable. Setting this bit will enable the issuance
of Remote Busy Indication primitives (PPRIM=5) upon reception of
RNR or RR frame indicating a change in the busy status of the remote.
Receive frames with Bad FCS. Setting this bit causes the MK50H25 to
receive frames with bad FCS when in Transparent Mode. The FRMRR
bit in RMD0 will be set to indicate the received frame had a bad FCS.
This bit should be set only for Transparent Mode
FCSER. Setting this bit enables a separate Error Counter at IADR + 56
that will count aborted frames separately from Bad Frames Received.
Setting this bit will cause the MK50H25 to append the entire FCS of
received frames to the receive data buffer, and MCNT will reflect the
additional FCS bytes.
RECEIVE DESCRIPTOR RING ADDRESS is the base address
(lowest address) of the Receive Descriptor Ring. The Receive De-
scriptor Address must begin on a word boundary.
DESCRIPTION
Reserved, must be written as a zero.
1
4
RLEN
TLEN
1
3
1
3
1
2
1
2
R
B
S
Y
1
1
1
1
0
1
0
R
B
F
C
S
1
0
RDRA<15:00>
TDRA<15:00>
TWD
0
9
F
C
S
E
R
0
9
0
8
F
C
S
E
N
0
8
0
7
0
7
0
6
0
6
RDRA<23:16>
0
5
TDRA<23:16>
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
0
MK50H25
33/64