MK50H25DIP ST Microelectronics, Inc., MK50H25DIP Datasheet - Page 38

• Manufacturer Part Number: MK50H25DIP
• Description: High Speed Link Level Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H25
4.3.2.2 Transmit Message Descriptor 1 (TMD1)
4.3.2.3 Transmit Message Descriptor 2 (TMD2)
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11
10
09
08
07:00
BIT
15:00
BIT
15:00
TUI
TINTD
0
XPF
TBADR
NAME
TBADR
NAME
BCNT
1
5
1
5
1
4
1
4
1
3
1
3
Transmit a UI frame indicates that a UI frame is to be transmitted from
the transmit buffer instead of a normal I frame. This bit must be set
for anything transmitted in Transparent Mode.
Transmit Interrupt Disable. If this bit is set, no transmit interrupt is
generated when ownership of this descriptor is released back to the
host.
Reserved, must be written as zeroes.
Transmit P/F bit instructs the MK50H25 to send the corresponding frame
with the respective value for the P/F bit. This bit is valid is valid only for
UI, XID and TEST frames and should be written zero otherwise.
The High Order 8 address bits of the buffer pointed to by this descriptor.
This field is written by the Host and unchanged by MK50H25.
DESCRIPTION
The Low Order 16 address bits of the buffer pointed to by this descriptor.
TBADR is written by the Host and unchanged by MK50H25. The least
significant bit is zero since the descriptor must be word aligned.
DESCRIPTION
Buffer Byte Count is the usable length of the buffer pointed to by this
descriptor expressed in two’s complement. This field is not used by
the MK50H25.
1
2
1
2
1
1
1
1
1
0
1
0
TBADR<15:00>
0
9
0
9
BCNT<15:00>
0
8
0
8
0
7
0
7
0
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0