MK50H25DIP ST Microelectronics, Inc., MK50H25DIP Datasheet - Page 34

• Manufacturer Part Number: MK50H25DIP
• Description: High Speed Link Level Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H25
4.2.7 XID/TEST Descriptors
The XID/TEST Descriptors contain pointers to the buffers used to receive and transmit XID, and TEST
frames, as well as buffer lengths. The exact format of these descriptors can be seen in the following Re-
ceive and Transmit Message Descriptor Entry descriptions. They are used the same as other descriptors
except that no data chaining is allowed (i.e., SLF and ELF must be set to 1).
4.2.8 Status Buffer Address
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14:12
11
10:08
07:00/15:00
BIT
15:08
07:00/15:00
TLEN
IADR + 40
IADR + 42
0
TWD
TDRA
NAME
0
SBA
1
5
power of two less one. TWD is the maximum number of I frames which
may be transmitted without an acknowledgement. TWD is not allowed
to be greater than 127. For Transparent Mode set TWD = 1 or more.
(lowest address) of the Transmit Descriptor Ring. The Transmit De-
scriptor Ring Address must begin on a word boundary.
buffer into which status information is placed upon the issuance of the
Status Request primitive by the HOST. The status buffer must begin
on a word boundary.
TRANSMIT RING LENGTH is the number of entries in the Transmit
Ring expressed as a power of two.
Reserved, must be written as a zero.
Transmit Window is the window size of the Transmitter expressed as a
TRANSMIT DESCRIPTOR RING ADDRESS is the base address
DESCRIPTION
Reserved, must be written as zeroes.
STATUS BUFFER ADDRESS points to a 7 word status
1
4
(If CSR2 EIBEN =1)
TLEN
1
3
0
1
2
3
4
5
6
7
1
2
N 2
1
1
0
0
NUMBER
ENTRIES
SBA<15:00>
0
9
128
OF
16
32
64
1
2
4
8
0
8
0
7
TWD
0
6
0
1
2
3
4
5
6
7
0
5
SBA<23:16>
0
4
EXTC = 0
0
3
NA
WINDOW SIZE
1
2
3
4
5
6
7
0
2
0
1
EXTC = 1
0
0
0
127
127
15
31
63
1
3
7