MK50H25DIP ST Microelectronics, Inc., MK50H25DIP Datasheet - Page 4

• Manufacturer Part Number: MK50H25DIP
• Description: High Speed Link Level Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H25
TAble 1: PIN DESCRIPTION
LEGEND:
I
IO
OD
Note:
4/64
SIGNAL NAME
DAL<15:00>
BUSAKO
BUSREL
READ
DALO
BYTE
INTR
DALI
BMO
DAS
BM1
Open Drain (no internal pull-up)
Pin out for 52 pin PLCC is shown in brackets.
Input / Output
Input only
PIN(S)
44-51]
40-47
[2-10
[11]
[12]
[13]
[14]
[15]
[16]
[18]
2-9
16
10
11
12
13
14
15
TYPE
IO/3S
IO/3S
O/OD
IO/3S
IO/3S
O/3S
O/3S
O/3S
DATA STROBE defines the data portion of a bus transaction. By definition,
data is stable and valid at the low to high transition of DAS. This signal is
driven by the MK50H25 while it is the BUS MASTER. During the BUS
SLAVE operation, this pin is used as an input. At all other times the signal is
tristated.
I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set
to a one, pin 15 becomes input BUSREL and is used by the host to signal
the MK50H25 to terminate a DMA burst after the current bus transfer has
completed. If bit 06 is clear then pin 15 is an output and behaves as
described below for pin 16.
Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON).
BYTE MASK<1:0> Indicates the byte(s) on the DAL to be read or written
during this bus transaction. MK50H25 drives these lines only as a Bus
Master. MK50H25 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
BM1
LOW
LOW
HIGH
HIGH
The time multiplexed Data/Address bus. During the address portion of a
memory transfer, DAL<15:00> contains the lower 16 bits of the memory
address.
During the data portion of a memory transfer, DAL<15:00> contains the read
or write data, depending on the type of transfer.
READ indicates the type of operation that the bus controller is performing
during a bus transaction. READ is driven by the MK50H25 only while it is the
BUS MASTER. READ is valid during the entire bus transaction and is
tristated at all other times.
MK50H25 as a Bus Slave :
READ = HIGH - Data is placed on the DAL lines by the chip.
READ = LOW - Data is taken off the DAL lines by the chip.
MK50H25 as a Bus Master :
READ = HIGH - Data is taken off the DAL lines by the chip.
READ = LOW - Data is placed on the DAL lines by the chip.
INTERRUPT is an attention interrupt line that indicates that one or more of
the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT.
INTERRUPT is enabled by CSR0<09>, INEA=1.
DAL IN is an external bus transceiver control line. DALI is driven by the
MK50H25 only while it is the BUS MASTER. DALI is asserted by the
MK50H25 when it reads from the DAL lines during the data portion of a
READ transfer. DALI is not asserted during a WRITE transfer.
DAL OUT is an external bus transceiver control line. DALO is driven by the
MK50H25 only while it is the BUS MASTER. DALO is asserted by the
MK50H25 when it drives the DAL lines during the address portion of a READ
transfer or for the duration of a WRITE transfer.
If CSR4<00> BCON = 0,
O
3S
LOW
HIGH
LOW
HIGH
BM0
I/O PIN 16 = BM1 (O/3S)
I/O PIN 15 = BMO (O/3S)
3-State
Output only
TYPE OF TRANSFER
UPPER BYTE
ENTIRE WORD
(DAL<15:08>)
(DAL<07:00>)
NONE
LOWER BYTE
DESCRIPTION