MK50H25DIP ST Microelectronics, Inc., MK50H25DIP Datasheet - Page 52

• Manufacturer Part Number: MK50H25DIP
• Description: High Speed Link Level Controller
• Manufacturer: ST Microelectronics, Inc.

Figure 7: MK50H25 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>)
DAL0-15
SYSCLK
A 16-23
READY
HOLD
HLDA
DALO
BM0,1
READ
DALI
ALE
DAS
NOTES:
1. The shaded SYSCLK periods T0 and T5 will be removed when setting CSR2 bit 15,
2. Output delay times are the maximum delay from the specifed edge to a valid output.
3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments
CYCLE =1 to select the shorter DMA cycle as shown in Figure 7a.
until the slave device returns READY.
24
64
45
27
23
23
T 0
49
25
29
T 1
ADDR
50
T 2
46
40
T 3
30
ADDRESS
60
43
T 4
44
T 5
31
61
DATA IN
T 6
28
32
47
26
41
65
42
22
48
48
MK50H25
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