k4d551638h Samsung Semiconductor, Inc., k4d551638h Datasheet - Page 10

• Manufacturer Part Number: k4d551638h
• Description: 256mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

7.4 WRITE INTERRUPTED BY A READ & DM
K4D551638H
The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow
4. If input Write data is masked by the Read command, the DQS input is ignored by the GDDR.
* This function is only supported in 200/166MHz.
8.0 ABSOLUTE MAXIMUM RATINGS
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Voltage on any pin relative to Vss
Voltage on V
Voltage on V
Storage temperature
Power dissipation
Short circuit current
cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any
residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to
avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be
written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
is 1 clock cycle is disallowed
Read operation and the input data word which immediately follows the interrupting Read operation
the buses to turn around before the GDDR drives them during a read operation.
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock
CAS Latency=3
CAS Latency=3
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DD
DD
< Burst Length=8, CAS Latency=3 >
Parameter
supply relative to Vss
supply relative to Vss
Command
DQS
DQ ′s
DQS
DQ ′s
CK
CK
DM
NOP
0
t
WPRES*
t
WRITE
WPRES*
5
t
DQSSmin
1
t
DQSSmax
5
Din 0
NOP
V
Symbol
IN
Din 0
Din 1
V
T
V
2
, V
I
P
DDQ
STG
OS
DD
D
OUT
Din 1
Din 2
- 10 -
NOP
Din 2
Din 3
3
Din 3
Din 4
NOP
t
CDLR
Din 4
Din 5
t
CDLR
4
Din 5
Din 6
-55 ~ +150
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
READ
Value
Din 6
Din 7
2.0
50
5
256M GDDR SDRAM
Din 7
NOP
6
Rev. 1.3 April 2007
NOP
7
Unit
mA
°C
W
V
V
V
NOP
Dout 0 Dout 1
Dout 0 Dout 1
8