k4d551638h Samsung Semiconductor, Inc., k4d551638h Datasheet - Page 7

• Manufacturer Part Number: k4d551638h
• Description: 256mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

* When the operating frequency is changed, DLL reset should be required again.
K4D551638H
7.0 FUNCTIONAL DESCRIPTION
7.1 Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
Command
*1
*
Power up & Initialization Sequence
1,2
CK,CK
stable for 200us
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
7. Issue precharge command for all banks of the device.
Inputs must be
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
- Apply V
- Apply V
0
ALL Banks
precharge
DD
DDQ
1
before V
before V
2
t
RP
DDQ
3
REF
EMRS
.
& V
4
2 Clock min.
TT
5
DLL Reset
MRS
6
2 Clock min.
7
ALL Banks
precharge
8
- 7 -
9
tRP
10
1st Auto
Refresh
200 Clock min.
11
t
12
RFC
13
2nd Auto
Refresh
256M GDDR SDRAM
14
15
t
RFC
16
Rev. 1.3 April 2007
17
Register Set
Mode
18
2 Clock min.
19
Command
Any