k4d551638h Samsung Semiconductor, Inc., k4d551638h Datasheet - Page 9

• Manufacturer Part Number: k4d551638h
• Description: 256mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4D551638H
7.3 EXTENDED MODE REGISTER SET(EMRS)
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL.
The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A12 and
BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting
driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended
mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as
long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
RFU
BA1
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the
*1
BA
0
1
BA0
1
0
EMRS
A12
A
MRS
n
~ A
0
A11
A10
A9
A8
A1
0
1
RFU
A7
Output Driver Impedence Control
*1
Weak
Full
A6
- 9 -
A5
A4
100%
60%
A3
A2
256M GDDR SDRAM
D.I.C
A1
DLL
Rev. 1.3 April 2007
A0
A
0
1
0
Address Bus
Extended
Mode Register
DLL Enable
Disable
Enable