k4d551638h Samsung Semiconductor, Inc., k4d551638h Datasheet - Page 5

• Manufacturer Part Number: k4d551638h
• Description: 256mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4D551638H
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
LDQS,UDQS
DQ0 ~ DQ15
V
LDM,UDM
BA0, BA1
CK, CK
A0 ~ A12
V
DDQ
NC/RFU
Symbol
For any applications using the single ended clocking, apply V
DD
V
CKE
RAS
CAS
WE
CS
REF
/V
/V
SS
SSQ
*1
Reserved for future use
No connection/
Power Supply
Power Supply
Power Supply
Input/Output
Input/Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.CKE is synchronous
for Power down entry and exit, and for Self refresh entry. CKE is asynchronous for Self
refresh exit, and for output disable. CKE must be maintained high through Read and Write
accesses. Input buffers, excluding CK, CK and CKE are disbled during Power down. Input
buffers, excluding CKE are disabled during Self refresh. CKE is an SSTL_2 input, but will
detect a LVCMOS low level after Vdd is applied upon 1st power up. After Vref has become
stable during the power on and intialization sequence, it must be maintained for proper oper-
ation of the CKE receiver. For proper Self refresh entry and exit, Vref must be maintained to
this input.
CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
Latches row addresses on the positive going edge of the CK with RAS low. Enables row
access & precharge.
Latches column addresses on the positive going edge of the CK with CAS low. Enables col-
umn access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on
DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons
to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
REF
to CK pin.
- 5 -
Function
256M GDDR SDRAM
Rev. 1.3 April 2007