com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 26

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

4, 3 Extended
BIT
7
6
5
16-Bit Enable
Command
Chaining Enable
Decode Mode
Timeout 1, 2
BIT NAME
SYMBOL
16EN
CCHEN
DECODE In I/O Mapped applications, this bit is used to choose
ET1, ET2 These bits allow the network to operate over longer distances
Table 8 - Configuration Register
This bit, if high, enables 16-bit operation of the device. A low
level on this bit enables only 8-bit operation. This bit defaults
to a logic "0" upon hardware reset.
This bit, if high, enables the Command Chaining operation of
the device. Please refer to the Command Chaining section of
this document for further details.
ensures software compatibility with previous SMSC ARCNET
devices. This bit defaults to a logic "0" upon hardware reset.
between an 8K or 16K block of ROM. In this case, a logic "0"
defines 8K, while a logic "1" defines 16K. In Memory Mapped
applications, this bit and the nENROM input are used to
choose whether the nMEMCS16 signal will be generated by
decoding a block of 128K or 2K. In this case, a logic "0"
defines 128K, while a logic "1" defines 2K. For more details
on the use of this bit, refer to the Memory vs. I/O Cycles
section of this document. This bit defaults to a logic "0" upon
hardware reset.
than the default four miles by controlling the Response Time,
the Idle Time, and the Reconfiguration Time.
network operation, all nodes should be configured for the
same timeout values. The bit combinations follow:
ET2 ET1 TIME (µs) TIME (µs)
These bits default to a logic "1" upon hardware reset.
0
0
1
1
0
1
0
1
26
RESPONSE
1193.6
596.8
298.4
74.7
DESCRIPTION
1312
656
328
82
IDLE
RECONFIGURATION
A low level on this bit
1680
1680
1680
840
TIME (mS)
For proper