com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 36
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com90c66
Manufacturer Part Number
com90c66
Description
Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
Manufacturer
Standard Microsystems Corp.
Datasheet
1.COM90C66.pdf
(76 pages)
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Internal POR
nMEMR, nMEMW,
Internal Reset
Hardware or
Software Reset
Microsequencer POR
nIOR, nIOW
3
1 During this time, the microsequencer is being reset and the transmitter
2 During this time, the microsequencer writes D1H to address 00H, and the Node
portion of the device is disabled.
During this time, the nTOPH, nTOPL, nPROM, nIOCS16, and nMEMCS16 signals are a
ID number to 01H. The transmitter portion of the device is enabled.
a logic "1"; the INTR signal is a logic "0"; the data bus is in the high
impedance state; and the IOCHRDY signal is in normal operation.
FIGURE 10 - INTERNAL RESET SEQUENCE
256 bit clocks
102.4 uS or
1
36
3
The 2nd cycle should be
issued after the 12uS.
12 uS
2
Enabled
Cycles