com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 32

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

of a dual two-level FIFO, commands to be
transmitted and received, as well as the status
bits, are pipelined.
In order for the COM90C66 to be compatible with
previous SMSC ARCNET devices, the device
defaults to the non-chaining mode. In order to
take advantage of the Command Chaining
operation, the Command Chaining Mode must be
enabled via a logic "1" on bit 6 of the
Configuration Register.
The following is a list of Command Chaining
guidelines for the software programmer to follow.
Command Chaining and Receive Command
Chaining sections of this document.
Further detail can be found in the Transmit
The device is designed such that the
interrupt service routine latency does not
affect performance.
maybe serviced prior to the generation of the
second interrupt.
TRI
TRI
RI
The first interrupt
TA
POR
32
TEST
In Command Chaining, the Status Register looks
as follows:
Up to two outstanding transmissions and two
Up to two outstanding transmit interrupts
The Interrupt Mask bits act on TTA (Rising
The traditional TA and RI bits are still
outstanding receptions can be pending at
any given time.
given in any order.
and two outstanding receive interrupts are
stored by the device, along with their
respective status bits.
Transition on Transmitter Available) for
transmit
Transition of Receiver Inhibited) for receive
operations. TTA is set upon completion of a
packet reception only. Typically there is no
need to mask the TTA and TRI bits after
clearing the interrupt.
available to reflect the present status of the
device.
RECON
operations
The commands may be
TMA
TMA
and
TRI
TTA
TTA
(Rising