com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 31

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

The fourth possibility is if a non-traditional
response is received (some pattern other than
ACK or NAK, such as noise). In this case, the
token is not passed onto the next node, which
causes the Lost Token Timer of the next node to
time
reconfiguration.
The DISABLE TRANSMITTER command may be
used to cancel any pending transmit command
when the COM90C66 next receives the token.
Normally, in an active network, this command
will set the TA status bit to a logic "1" when the
token
TRANSMITTER command does not cause the
TA bit to be set in the time it takes the token to
make a round trip through the network, one of
three situation exists.
disconnected from the network, or there are no
other nodes on the network, or the external
receive circuitry has failed. These situations can
be determined either by using the improved
diagnostic features of the COM90C66 or by using
another software timeout which is greater than
the worst cast time for a round trip token pass,
which occurs when all nodes transmit a
maximum length message.
Receive Sequence
A receive sequence begins with the RI status bit
becoming a logic "1", which indicates that a
previous
microprocessor
corresponding bit in the Interrupt Mask Register
is set to logic "1". Otherwise, the microprocessor
must periodically check the Status Register.
Once the microprocessor is alerted to the fact
that the previous reception has concluded, it may
issue the ENABLE RECEIVE TO PAGE nn
command, which resets the RI bit to logic "0" and
selects a new page in the RAM buffer. Again, the
appropriate buffer size is specified in the DEFINE
CONFIGURATION command.
page which just received the data packet will be
read by the microprocessor at this point.
out,
is
reception
received.
thus
will
generating
has
be
Either the node is
If
interrupted
concluded.
the
Typically, the
a
DISABLE
network
if
The
the
31
Once the ENABLE RECEIVE TO PAGE nn
command is issued, the microprocessor attends
to other duties. There is no way of telling how
long the new reception will take, since another
node may transmit a packet at any time. When
another node does transmit a packet to this
node,
command has enabled the reception of long
packets, the COM90C66 interprets the packet as
a long or short packet, depending on whether the
content of the buffer location 2 is zero or non-
zero. The format of the buffer is shown in Figure
9.
(SID), Address 1 contains the Destination
Identifier (DID), and address 2 contains, for short
packets, the value 256-N, where N represents the
message length, or for long packets, the value 0,
indicating that it is indeed a long packet. In the
latter case, Address 3 contains the value 512-N,
where N represents the message length. Note
that on reception the COM90C66 deposits
packets into the RAM buffer in the same format
that the transmitting node arranged it, which
allows for a message to be received and then
retransmitted without rearranging any bytes in
the RAM buffer other than the SID and DID.
Once the packet is received and stored correctly
in the selected buffer, the COM90C66 sets the RI
bit to logic "1" to signal the microprocessor that
the reception is complete.
SOFTWARE COMPATIBILITY
CONSIDERATIONS
The COM90C66 guarantees compatibility with
previous SMSC ARCNET devices.
hardware
compatibility mode, that is, 8-bit, memory
mapped cycles, non-Command Chaining mode
and non-Zero Wait State mode.
COMMAND CHAINING
The
consecutive transmissions and receptions to
occur without host intervention. Through the use
Address 0 contains the Source Identifier
Command
if
reset,
the
DEFINE
Chaining
the
device
CONFIGURATION
operation
defaults
allows
Upon
to