com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 63

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

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Description of Pin Functions - n0WS
Figure 2 - Bus Interface
Tables 3, 4, 8 - Configuration
Register Bit 7 (16EN) and Bit 5
(DECODE); Tables 11, 12; Figure 12
Command Chaining section
READ AND WRITE CYCLES -
Memory vs. I/O Cycles section
Wait State Details section; Table 13
8-Bit vs. 16-Bit Accesses section
Table 14
Figure 14
Figure 26
DATA SHEET ERRATA FOR REVISION B COM90C66
SECTION/FIGURE/ENTRY
63
Make no connection to this pin.
16-Bit Interface Signals must always be present.
Bit 7 (16-Bit Enable) of the Configuration
Register must be written to as a logic "1" for
proper
Configuration Register (Decode Mode) is not
effective.
The status bits are only single-level.
In I/O Mapped Mode, packets in the internal
RAM buffer must be accessed by addressing
one 16-bit I/O location.
mode increments the pointer by two. The device
should not be used in 8-bit mode.
The Wait State bit may be written to as a logic
"0" to avoid IOCHRDY negation, but the n0WS
signal must be left disconnected.
Disregard references to 8-bit Memory and 8-bit
I/O Mapped Mode.
memory should be 16-bit. When the device is in
16-bit I/O Mapped Mode, byte writes to odd
locations should not be done.
8-bit I/O accesses to the Data Register and 8-bit
Memory accesses should not be done.
Disregard the n0WS timing signal. This signal
should not be used.
t3 should read 314 µsec minimum.
The n0WS signal should be left disconnected.
device
CORRECTION
operation.
All accesses to internal
The device in 16-bit
Bit
5
of
the