dq8051xp Digital Core Design, dq8051xp Datasheet - Page 5
dq8051xp
Manufacturer Part Number
dq8051xp
Description
Manufacturer
Digital Core Design
Datasheet
1.DQ8051XP.pdf
(11 pages)
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operation with Internal or External Program
Memory. Program Memory can be imple‐
mented as ROM, RAM or FLASH.
PROGRAM
INTERNAL
Memory of up to 256 bytes The Internal Data
Memory can be implemented as synchronous
RAM.
EXTERNAL
16 MB of External Data Memory. Extra DPX
(Data Pointer eXtended) register is used for
segments swapping.
SYNCHRONOUS
64 kB of fast on‐chip Synchronous External
Data Memory. All reads and writes are exe‐
cuted in one clock cycle.
USER
tion Registers (ESFRs) may be added to the
DQ8051XP design. ESFRs are memory
mapped into Direct Memory between ad‐
dresses 0x80 and 0xFF in the same manner
as core SFRs and may occupy any address
that is not occupied by a core SFR.
WAIT
operation with wide range of Program and
Data memories. Slow Program and Exter‐
nal Data memory may assert a memory
Wait signal to hold up CPU activity.
The DQ8051XP soft core is dedicated for
The DQ8051XP can address Internal Data
The DQ8051XP soft core can address up to
The DQ8051XP soft core can address up to
The DQ8051XP soft core is dedicated for
Up to 60 External (user) Special Func‐
D E S I G N F E A T U R E S
SPECIAL
STATES
DATA
DATA
MEMORY:
SUPPORT:
FUNCTION
XDM:
MEMORY:
MEMORY:
All trademarks mentioned in this document are trademarks of their respective owners.
REGISTERS:
Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
port0i
port1i
port2i
port3i
idmdatai
sfrdatai
prgdatai
prgrdy
xdatai
xdatardy
sxdmdatai
int0
int1
int2
int3
int4
int5
int6
t0
gate0
t1
gate1
t2
t2ex
capture0
capture1
capture2
capture3
rxd0i
rxd1i
scli
sdai
ss
si
mi
scki
reset
clk
S Y M B O L
sxdmdatao
idmwaddr
sxdmaddr
idmdatao
idmraddr
debugacs
sfrwaddr
prgdatao
xaddress
prgdataz
sxdmwe
sfrdatao
xdatawr
sfrraddr
coderun
prgaddr
sxdmoe
xdatard
ramwe
port0o
port1o
port2o
port3o
xdatao
ramoe
xdataz
prgwr
rxd0o
rxd1o
sfrwe
scken
prgrd
pmm
sfroe
sclhs
sdao
soen
stop
txd0
txd1
scko
sclo
rsto
sso
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