dq8051xp Digital Core Design, dq8051xp Datasheet - Page 6

• Manufacturer Part Number: dq8051xp
• Manufacturer: Digital Core Design

idmwaddr
idmdatao
idmraddr
prgdatao
sfrwaddr
capture0
capture1
capture2
capture3
prgdataz
xaddress
xdatardy
idmdatai
prgdatai
sfrdatao
xdatawr
sfrraddr
prgaddr
xdatard
sfrdatai
xdatao
idmwe
prgrdy
xdataz
idmoe
xdatai
prgwr
rxd1o
prgrd
sfrwe
sfroe
rxd1i
sclhs
sdao
reset
t2ex
txd1
sclo
sdai
B L O C K D I A G R A M
rsto
scli
clk
t2
Point Unit
interface
Program
memory
interface
interface
interface
Compare
Slave I2C
memory
Memory
MDU32
decoder
External
Floating
Capture
Master/
Opcode
Control
Internal
Timer 2
UART 1
SFR’s
data
Data
User
Unit
Unit
All trademarks mentioned in this document are trademarks of their respective owners.
Debug Unit
Watchdog
controller
interface
Interrupt
registers
SPI Unit
I/O Port
DoCD™
UART 0
Timers
PMM
SXDM
Timer
Unit
ALU
Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
port0
port1
port2
port3
t0
t1
gate0
gate1
int0
int1
int2
int3
int4
int5
int6
pmm
stop
tdi
tck
tms
tdo
rtck
coderun
debugacs
rxd0o
rxd0i
txd0
so
si
mo
mi
scko
scki
scken
ss
sso
soen
clk
reset
port0i
port1i
port2i
port3i
prgdatai
prgrdy
sxdmdatai
xdatai
xdatardy
idmdatai
sfrdatai
int0
int1
int2
int3
int4
int5
int6
t0
t1
t2
gate0
gate1
t2ex
capture0
capture1
capture2
capture3
rxdi0
rxdi1
scli
sdai
ss
si
mi
scki
tdi
tck
tms
PIN
P I N S D E S C R I P T I O N
TYPE
input Global clock
input Global reset
input Port 0 input
input Port 1 input
input Port 2 input
input Port 3 input
input Data bus from program memory
input Program memory ready
input
input Data bus from external memories
input External data memory ready
input Data bus from internal data memory
input Data bus from user SFR’s
input External interrupt 0
input External interrupt 1
input External interrupt 2
input External interrupt 3
input External interrupt 4
input External interrupt 5
input External interrupt 6
input Timer 0 input
input Timer 1 input
input Timer 2 input
input Timer 0 gate input
input Timer 1 gate input
input Timer 2 gate input
input Timer 2 capture 0 line
input Timer 2 capture 1 line
input Timer 2 capture 2 line
input Timer 2 capture 3 line
input Serial receiver input 0
input Serial receiver input 1
input Master/Slave I2C clock line input
input Master/Slave I2C data input
input SPI slave select
input SPI slave input
input SPI master input
input SPI clock input
input DoCD™ TAP data input
input DoCD™ TAP clock input
input DoCD™ TAP mode select input
Data bus from synchronous external
data memory (SXDM)
DESCRIPTION