dq8051xp Digital Core Design, dq8051xp Datasheet - Page 2

• Manufacturer Part Number: dq8051xp
• Manufacturer: Digital Core Design

80C51
DQ8051
DQ8051+DPTRs
DQ8051+DPTRs+SXDM
DQ8051+DPTRs+SXDM+MDU32
●
●
●
rameter is real application speed improvement
comparing to well known 80C51 architecture. The
Dhrystone Benchmark Version 2.1 was used to
measure 80C51 and DQ8051XP core performance.
The following table gives a survey about the
DQ8051XP performance in terms of Dhrystone
VAX MIPS per 1 MHz and its improvement compar‐
ing to 80C51.
ters
with no internal tri‐states
25
20
15
10
One of the most important performance pa‐
5
0
Interface for additional Special Function Regis‐
Fully synthesizable, static synchronous design
Scan test ready
VAX MIPS ratio
Core performance in terms of DMIPS per MHz
P E R F O R M A N C E
1
Device
80C51
DQ8051
DQ8051+DPTRs
DQ8051+DPTRs+SXDM
DQ8051+DPTRs+SXDM+MDU32
19,69
23,77
All trademarks mentioned in this document are trademarks of their respective owners.
25,13
DMIPS/MHz
0,00941
0,18527
0,22369
0,23650
0,25053
Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
26,62
Ratio
19,69
23,77
25,13
26,62
1,00
DQ8051XP core area in ASICs Devices (CPU fea‐
tures and peripherals have been included):
DQ8051 core area and performance in ASIC devices. Results given for
working system with two DPTRs and connected 256B IDM, 8kB CODE
and 2kB SXDM memories.
core in vendor specific technologies is summarized
in table below.
*CPU – consisted of ALU, Opcode Decoder, Control Unit, User SFRs interface,
IDM interface, XDM interface and Code Memory interface.
●
0,35 um
0.25 um
0.18 um
0.13 um
0.09 um
CPU*
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR’s auto‐switch and auto‐update
SXDM
Timed Access protection
Interrupt Controller
INT2‐INT6
Power Management Unit
I/O ports
Timers
Timer 2
UART0
UART1
Master I2C Unit
Slave I2C Unit
SPI Unit
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit 32
Total area
○
○
The following tables give a survey about the
Area utilized by the each unit of DQ8051XP
Device
DoCD™ debug unit
Processor execution control
Read‐write all processor contents
○
○
○
○
Run, Halt
Step into instruction
Skip instruction
Program Counter (PC)
P E R I P H E R A L S
Core components area utilization
Component
Speed
typical
typical
typical
typical
typical
21600 gates
20800 gates
19600 gates
20100 gates
18900 gates
Min area
120 MHz
170 MHz
250 MHz
430 MHz
70 MHz
F
Area
[Gates]
max
18900
7250
1200
1000
2900
400
150
150
250
200
700
700
800
800
650
800
650
50
50
75
50
75