ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 12

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

2.0 Signal Description
2.1 Local CPU Bus Interface Signals Group
SA[9:1],
SA[0]/LDS
/BHE
or
/UDS
SD[15:0]
IREQ/IREQ
RDY/DTACK
/CS
/IORD
/IOWR
or
R/W
/IOCS16
AEN
or
/PSEN
Tab - 1 Local CPU bus interface signals group
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
The following terms describe the AX88796 pin-out:
SIGNAL
TRI
I/O
O
I
AX88796 L
Input
Output
Input/Output
TRI-state
TRI/PU
TRI/PU
I/O/PD
TYPE
I/PU
I/PU
I/PU
I/PU
I/PD
O
I
PIN NO.
23 – 26,
35 – 39,
29 – 33,
41 – 42
12 – 4
128
123
15,
22
16
19
18
2
1
Bus High Enable or Upper Data Strobe : Bus High Enable is active
Interrupt Request : When ISA BUS or 80186 CPU mode is select.
Ready : This signal is set low to insert wait states during Remote
Chip Select
I/O Read :The host asserts /IORD to read data from AX88796 I/O
I/O Write :The host asserts /IOWR to write data into AX88796 I/O
I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the
Address Enable : The signal is asserted when the address bus is
System Address : Signals SA[9:0] are address bus input lines, which
lower I/O spaces on chip. SA[0] also means Lower Data Strobe
(/LDS) active low signal in 68K application mode.
low signal in some 16-bit application mode, which enable high bus
(SD[15:8]) active. The signal also name as Upper Data Strobe (/UDS)
for 68K application mode.
System Data Bus : Signals SD[15:0] constitute the bi-directional data
bus.
IREQ is asserted high to indicate the host system that the chip requires
host software service. When MC68K or MCS-51 CPU mode is select.
/IREQ is asserted low to indicate the host system that the chip requires
host software service.
DMA transfer.
/Dtack : When Motorola CPU type is selected, the pin is active low
inform CPU that data is accepted.
When the /CS signal is asserted, the chip is selected.
space. When Motorola CPU type is select , the pin is useless.
space. When Motorola CPU type is select, the pin is active high for
read operation at the same time.
range corresponds to an I/O address to which the chip responds, and
the I/O port addressed is capable of 16-bit access.
available for DMA cycle. When negated (low), AX88796 an I/O slave
device may respond to addresses and I/O command.
PSEN : This signal is active low for 8051 program access. For I/O
device, AX88796, this signal is active high to access the chip. This
signal is for 8051 bus application only.
3-in-1 Local Bus Fast Ethernet Controller
12
PU
PD
P
DESCRIPTION
ASIX ELECTRONICS CORPORATION
Internal Pull Up(200K)
Internal Pull Down(50K)
Power Pin