ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 14

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

2.4 EEPROM Signals Group
EECS
EECK
EEDI
EEDO
Tab - 4 EEPROM bus interface signals group
2.5 MII interface signals group (Optional)
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
Tab - 5 MII interface signals group
SIGNAL
SIGNAL
AX88796 L
I/O/PU
(Omit)
TYPE
TYPE
O/PD
O/PU
I/PU
I/PU
I/PD
I/PD
I/PU
I/PD
I/PU
O
O
O
O
No Support Receive Error : RX_ER ,is driven by PHY and synchronous to
112 – 109
PIN NO.
PIN NO.
98 – 95
100
102
101
108
107
51
50
49
48
99
67
66
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO. All
data transfers on MDIO are synchronized to the rising edge of this
clock. The signal output reflects MDC register value. About MDC
register, please refer to MII/EEPROM Management register bit 0.
MDC clock frequency is a 2.5MHz maximum accourding to IEEE
802.3u MII specification. Acturely, many PHYs are designed to
accept
higher frequency than 2.5MHz.
Station Management Data Input/Output :Serial data input/output
transfers from/to the PHYs . The transfer protocol has to meet the
IEEE 802.3u MII specification. For more information, please refer to
section 6.5 CPU Access MII Station Management functions.
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
3-in-1 Local Bus Fast Ethernet Controller
14
DESCRIPTION
DESCRIPTION
ASIX ELECTRONICS CORPORATION