ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 50

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

31.15 (ERROR)
31.14
(RXERR_ST)/(LINK_ST
AT_CHANGE)
31.13 (REM_FLT)
31.12
(UNLOCKED)/(JABBE
R)
31.11 (LSTAT_OK)
31.10 (PAUSE)
31.9 (SPEED100)
31.8 (FULL_DUP)
31.7 (INT_CONF)
31.6 (INT_MASK)
31.5:3
(LOW_AUTO__STATE)
31.2:0
(HI_AUTO_STATE)
5.2.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions
FIELD
AX88796 L
TYPE
R/W
R/W
R
R
R
R
R
R
R
R
R
R
Receiver Error. When this bit is a 1, it indicates that a receive error has been
detected. This bit is valid in 100Mbits/s only. This bit will remain set until
cleared by reading the register. Default is a 0.
False Carrier. When bit [31.7] is set to 0 and this bit is a 1, it indicates that the
carrier detect state machine has found a false carrier. This bit is valid in
100Mbits/s only. This bit will remain set until cleared by reading the register.
Default is 0.
Link Status Change. When bit [31.7] is set to a 1, this bit is redefined to become
the LINK_STAT_CHANGE bit and goes high whenever there is a change in link
status (bit [31.11] changes state)
Remote Fault. When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. Default is a 0.
Unlocked/Jabber. If this bit is set when operating in 100Mbits/s mode, it
indicates that the TX descrambler has lost lock. If this bit is set when operating in
10Mbits/s mode, it indicates a jabber condition has been detected. This bit will
remain set until cleared by reading the register.
Link Status. When this bit is a 1, it indicates a valid link has been established.
This bit has a latching low function: a link failure will cause the bit to clear and
stay cleared until it has been read via the management interface.
Link Partner Pause. When this bit is set to a 1, it indicates that the LU3X54FTL
wishes to exchange flow control information.
Link Speed. When this bit is set to a 1, it indicates that the link has negotiated to
100Mbits/s. When this bit is a 0, it indicates that the link is operating at
10Mbits/s.
Duplex Mode. When this bit is set to a 1, it indicates that the link has negotiated
to full-duplex mode. When this bit is a 0, it indicates that the link has negotiated
to half-duplex mode.
Interrupt Configuration. When this bit is set to a 0, it defines bit [31.14] to be
the RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high
whenever any of bits [31.15:12] go high, or bit [31.11] goes low. When this bit is
set high, it redefines bit [31.14] to become the LINK_STAT_CHANGE bit, and
the interrupt pin (MASK_STAT_INT) goes high only when the link status
changes (bit [31.14] goes high). This bit defaults to 0.
Interrupt Mask. When set high, no interrupt is generated by this channel under
any condition. When set low, interrupts are generated according to bit [31.7].
Lowest Autonegotiation State. These 3 bits report the state of the lowest
autonegotiation state reached since the last register read, in the priority order
defined below:
000: Autonegotiation enable.
001: Transmit disables or ability detects.
010: Link status check.
011: Acknowledge detects.
100: Complete acknowledges.
101: FLP link good check.
110: Next page wait.
111: FLP link good.
Highest Autonegotiation State. These 3 bits report the state of the highest
autonegotiation state reached since the last register read, as defined above for bit
[31.5:3].
3-in-1 Local Bus Fast Ethernet Controller
50
DESCRIPTION
ASIX ELECTRONICS CORPORATION