ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 2

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

1.0 INTRODUCTION......................................................................................................................................................5
2.0 SIGNAL DESCRIPTION........................................................................................................................................12
3.0 MEMORY AND I/O MAPPING ............................................................................................................................18
4.0 BASIC OPERATION .............................................................................................................................................19
5.0 REGISTERS OPERATION....................................................................................................................................32
1.1 G
1.2 AX88796 B
1.3
1.3
2.1 L
2.2 10/100M
2.3 B
2.4 EEPROM S
2.5 MII
2.6 S
2.7 G
2.8 M
2.9 P
3.1 EEPROM M
3.2 I/O M
3.3 SRAM M
4.1 R
4.2 B
5.1 MAC C
1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode .....................................................................................8
1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode ........................................................................................9
1.3.3 AX88796 Pin Connection Diagram for MC68K Mode ...................................................................................10
1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode...................................................................................11
4.1.1 Unicast Address Match Filter .........................................................................................................................19
4.1.2 Multicast Address Match Filter.......................................................................................................................19
4.1.3 Broadcast Address Match Filter .....................................................................................................................20
4.1.4 Aggregate Address Filter with Receive Configuration Setup..........................................................................20
4.2.1 Packet Reception .............................................................................................................................................22
4.2.2 Packet Transmision .........................................................................................................................................25
4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory) .........................................................................27
4.2.4 Removing Packets from the Ring (Host read data from memory)...................................................................28
4.2.5 Other Useful Operations .................................................................................................................................31
5.1.1 Command Register (CR) Offset 00H (Read/Write) ........................................................................................33
5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)...............................................................................34
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write).........................................................................................35
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write) ...............................................................................35
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .........................................................................35
5.1.6 Transmit Status Register (TSR) Offset 04H (Read) ........................................................................................36
5.1.7 Receive Configuration (RCR) Offset 0CH (Write) .........................................................................................36
5.1.8 Receive Status Register (RSR) Offset 0CH (Read) .........................................................................................36
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write) ............................................................................................37
5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)......................................................................37
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)......................................................................37
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write).....................................................37
5.1.13 Test Register (TR) Offset 15H (Write)..........................................................................................................37
5.1.14 Test Register (TR) Offset 15H (Read) ..........................................................................................................38
A
B
AX88796 P
AX88796 P
TANDARD
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
OCAL
UILT
ECEIVER
UFFER
ENERAL
ENERAL
ISCELLANEOUS PINS GROUP
INTERFACE SIGNALS GROUP
-
APPING
AX88796 L
IN
CPU B
ORE
M
BPS
PHY LED
EMORY
D
P
F
ANAGEMENT
P
URPOSE
ESCRIPTION
ILTERING
LOCK
IGNALS
R
RINTER
EMORY
IN
IN
T
..........................................................................................................................................................18
EGISTERS
US
WISTED
C
C
ONNECTION
ONNECTION
I
M
D
NTERFACE
I/O
APPING
IAGRAM
G
P
M
INDICATOR PINS GROUP
..............................................................................................................................................19
ROUP
ORT
-P
APPING
: ...........................................................................................................................................5
PINS GROUP
O
..........................................................................................................................................32
AIR
PERATION
(SPP) I
.....................................................................................................................................14
.....................................................................................................................................18
: ....................................................................................................................................5
I
S
NTERFACE PINS GROUP
D
D
.................................................................................................................................16
................................................................................................................................18
IGNALS
IAGRAM WITH
IAGRAM
(O
NTERFACE PINS GROUP
PTIONAL
........................................................................................................................15
........................................................................................................................22
G
...................................................................................................................6
ROUP
3-in-1 Local Bus Fast Ethernet Controller
CONTENTS
) ..........................................................................................................14
..........................................................................................................13
SPP P
.......................................................................................................12
ORT
..............................................................................................13
2
O
(O
PTION
PTIONAL
............................................................................7
) ..................................................................15
...................................................................17
ASIX ELECTRONICS CORPORATION