ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 26

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

The AX88796 requires a contiguous assembled packet with the format shown. The transmit byte count
includes the Destination Address, Source Address, Length Field and Data. It does not include preamble and
CRC. When transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes.
The programmer is responsible for adding and stripping pad bytes. The packets are placed in the buffer RAM
by the system. System programs the AX88796 Core's Remote DMA to move the data from the data port to the
RAM handshaking with system transfers loading the I/O data port.
The data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the AX88796 Controller is set
in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register and setting
the
TRANSMISSION
Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count
Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is
set. The Transmit Status Register (TSR) is cleared and the AX88796 begins to prefetch transmit data from
memory. If the Interpacket Gap (IPG) has timed out the AX88796 will begin transmission.
CONDITIONS REQUIRED TO BEGIN TRANSMISSION
In order to transmit a packet, the following three conditions must be met:
1. The Interpacket Gap Timer has timed out
2. At least one byte has entered the FIFO. (This indicates that the burst transfer has been started)
3. If a collision had been detected then before transmission the packet backoff time must have timed out.
COLLISION RECOVERY
During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision
has occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the
Transmit DMA pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR
(Number of Collisions Register) will be incremented. If 15 retransmissions each result in a collision the
transmission will be aborted and the ABT bit in the TSR will be set.
Transmit Packet Assembly Format
The following diagrams describe the format for how packets must be assembled prior to transmission for
different byte ordering schemes. The various formats are selected in the Data Configuration Register and
setting the
CPU[1:0]
CPU[1:0]
AX88796 L
pins for ISA, 80186 or MC68K mode.
pins for ISA, 80186, MC68K or MCS-51 mode.
General Transmit Packet Format
D15
Destination Address
Source Address
Length / Type
Data
(Pad if < 46 Bytes)
Destination Address 1
Destination Address 3
Destination Address 5
3-in-1 Local Bus Fast Ethernet Controller
D8 D7
6 Bytes
6 Bytes
2 Bytes
46 Bytes
Min.
26
Destination Address 0
Destination Address 2
Destination Address 4
ASIX ELECTRONICS CORPORATION
D0