ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 25

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

6. Place the AX88796 in mode 1 loopback. This can be accomplished by setting bits D2 and D1, of the
7. Issue the START command to the AX88796. This can be accomplished by writing 22H to the Command
8. Remove one or more packets from the receive bufferring.
9. Reset the overwrite warning (OVW, overflow) bit in the Interrupt Status Register.
10. Take the AX88796 out of loopback. This is done by writing the Transmit Configuration Register with the
11. If the ``Resend'' variable is set to a 1, reset the ``Resend'' variable and reissue the transmit command. This
END OF PACKET OPERATIONS
At the end of the packet the AX88796 determines whether the received packet is to be accepted or rejected. It
either branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to
store the packet.
SUCCESSFUL RECEPTION
If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet
(pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next
packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are
discarded and reception of the next packet begins on the next empty 256 byte buffer boundary. The Current
Page Register is then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer
had been previously calculated and temporarily stored in an internal scratchpad register.)
BUFFER RECOVERY FOR REJECTED PACKETS
If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer
management logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR),
recovering all buffers that had been used to store the rejected packet. This operation will not be performed if
the AX88796 is programmed to accept either runt packets or packets with CRC or Frame Alignment errors.
The received CRC is always stored in buffer memory after the last byte of received data for the packet.
Error Recovery
If the packet is rejected as shown, the DMA is restored by the AX88796 by reprogramming the DMA starting
address pointed to by the Current Page Register.
The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer
during transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers
(TBCR0,1). When the AX88796 receives a command to transmit the packet pointed to by these registers,
buffer memory data will be moved into the FIFO as required during transmission. The AX88796 Controller
will generate and append the preamble, synch and CRC fields.
TRANSMIT PACKET ASSEMBLY
from the overflow routine, in order for the AX88796 to operate correctly.
Transmit Configuration Register to ``0,1''.
Register. This is necessary to activate the AX88796's Remote DMA channel.
value it contains during normal operation. (Bits D2 and D1 should both be programmed to 0.)
is done by writing a value of 26H to the Command Register. If the ``Resend'' variable is 0, nothing needs to
bedone.
4.2.2 Packet Transmision
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
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ASIX ELECTRONICS CORPORATION