gl848 Genesys Logic, gl848 Datasheet - Page 50

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gl848

Manufacturer Part Number
gl848
Description
High Speed Usb 2.0 2-in-1 Scanner Controller With Fast Adf & Bus Power
Manufacturer
Genesys Logic
Datasheet
©2000-2007 Genesys Logic Inc. - All rights reserved.
Offset 73h …….………………………..………..….………..….………..…..…. Default value = 8’h0A
CCD CP : CPH=0AH
Note: 16 clocks(phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode.
Offset 74h ……..……..………………..………..…...………..….………..…..…. Default value = 8’h00
Offset 75h ……..……..………………..……..…..….………..….………..…..…. Default value = 8’h00
Offset 76h ……..……..………………..………....….………..….………..…..…. Default value = 8’h00
Offset 77h ……..……..………………..………..…...………..….………..…..…. Default value = 8’h00
5
CK1MAP15 CK1MAP14 CK1MAP13 CK1MAP12 CK1MAP11 CK1MAP10 CK1MAP9 CK1MAP8
7-5 RESERVED
4-0 CPH [4:0]
7-5 RESERVED
4-0 CPL [4:0]
7-2 RESERVED
1-0
7-0 CK1MAP [15:8] Bits mapping setting for CCD clock 1 or 2.
7-0 CK1MAP [7:0] Bits mapping setting for CCD clock 1 or 2.
7-2 RESERVED
1-0
CK1MAP7 CK1MAP6 CK1MAP5 CK1MAP4 CK1MAP3 CK1MAP2 CK1MAP1 CK1MAP0
R/W
R/W
6 7
(1) Color, gray or line-art: 12 clocks(phase)/pixel
CK1MAP [17:16]
CK3MAP [17:16]
X
X
X
X
X
X
X
GL848 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF
8
R/W
R/W
9 10 11 0 1 2
X
X
X
X
X
X
X
-
Rising edge position of CCD CP.
-
Falling edge position of CCD CP.
-
Bits mapping setting for CCD clock 1 or 2.
-
Bits mapping setting for CCD clock 3.
CPL=01H
R/W
R/W
X
X
X
X
X
X
X
CPL4
R/W
R/W
3
R/W
R/W
X
X
X
X
4 5
CPL3
R/W
R/W
R/W
R/W
6 7
X
X
X
X
8
CPL2
R/W
R/W
R/W
R/W
9 10 11 0 1
X
X
X
X
CK1MAP17 CK1MAP16
CK3MAP17 CK3MAP16
CPL1
R/W
R/W
R/W
R/W
R/W
R/W
2 3
CPL0
Page 50
R/W
R/W
R/W
R/W
R/W
R/W
4

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