gl848 Genesys Logic, gl848 Datasheet - Page 51

• Manufacturer Part Number: gl848
• Description: High Speed Usb 2.0 2-in-1 Scanner Controller With Fast Adf & Bus Power
• Manufacturer: Genesys Logic

©2000-2007 Genesys Logic Inc. - All rights reserved.
Offset 78h ……..……..………………..……..…..….………..….………..…..…. Default value = 8’h00
Offset 79h ……..……..………………..………....….………..….………..…..…. Default value = 8’h00
Offset 7Ah ……..……..……………..………..…...………..….………..…..…. Default value = 8’h00
Offset 7Bh ……..……..………………..……..…..….………..….………..…..…. Default value = 8’h00
Offset 7Ch ……..……..……………..………....….………..….………..…..…. Default value = 8’h00
Offset 7Dh ……..……..………………..………..…………..….………..…..…. Default value = 8’h00
CK3MAP15 CK3MAP14 CK3MAP13 CK3MAP12 CK3MAP11 CK3MAP10 CK3MAP9 CK3MAP8
CK4MAP15 CK4MAP14 CK4MAP13 CK4MAP12 CK4MAP11 CK4MAP10 CK4MAP9 CK4MAP8
7-0 CK3MAP [15:8] Bits mapping setting for CCD clock 3.
7-0 CK3MAP [7:0] Bits mapping setting for CCD clock 3.
7-2 RESERVED
1-0 CK4MAP [17:16]
7-0 CK4MAP [15:8] Bits mapping setting for CCD clock 4.
7-0 CK4MAP[7:0] Bits mapping setting for CCD clock 4.
CK3MAP7 CK3MAP6 CK3MAP5 CK3MAP4 CK3MAP3 CK3MAP2 CK3MAP1 CK3MAP0
CK4MAP7 CK4MAP6 CK4MAP5 CK4MAP4 CK4MAP3 CK4MAP2 CK4MAP1 CK4MAP0
CK1NEG
7 CK1NEG
6 CK3NEG
5 CK4NEG
4 RSNEG
3 CPNEG
R/W
R/W
R/W
R/W
R/W
X
X
GL848 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF
CK3NEG
R/W
R/W
R/W
R/W
R/W
X
X
0 CCD clock1,clock2 output are synchronized with rising edge of system clock.
1 CCD clock1 & clock2 output are synchronized with falling edge of system clock.
0 CCD clock3 output is synchronized with rising edge of system clock.
1 CCD clock3 output is synchronized with falling edge of system clock.
0 CCD clock4 output is synchronized with rising edge of system clock.
1 CCD clock4 output is synchronized with falling edge of system clock.
0 CCD RS output is synchronized with rising edge of system clock.
1 RS output is synchronized with falling edge of system clock.
0 CCD CP output is synchronized with rising edge of system clock.
1 CCD CP output is synchronized with falling edge of system clock.
CK4NEG
-
Bits mapping setting for CCD clock 4.
R/W
R/W
R/W
R/W
R/W
X
X
RSNEG
R/W
R/W
R/W
R/W
R/W
X
X
CPNEG
R/W
R/W
R/W
R/W
R/W
X
X
BSMPNEG VSMPNEG
R/W
R/W
R/W
R/W
R/W
X
X
CK4MAP17 CK4MAP16
R/W
R/W
R/W
R/W
R/W
R/W
DLYSET
Page 51
R/W
R/W
R/W
R/W
R/W
R/W