A1240A-1CQ256B ACTEL [Actel Corporation], A1240A-1CQ256B Datasheet - Page 46
A1240A-1CQ256B
Manufacturer Part Number
A1240A-1CQ256B
Description
HiRel FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A1240A-1CQ256B.pdf
(98 pages)
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A 14 10 0A T i m i n g C h ar a c t er i st i c s
(W or st -C as e M il it ar y Cond it ion s, V
46
Parameter
CMOS Output Module Timing
t
t
t
t
t
t
t
t
d
d
d
d
Dedicated (Hard-Wired) I/O Clock Network
t
t
t
t
t
t
f
Dedicated (Hard-Wired) Array Clock Network
t
t
t
t
t
t
f
Notes:
1.
2.
DHS
DLS
ENZHS
ENZLS
ENHSZ
ENLSZ
CKHS
CKLS
IOCKH
IOPWH
IOPWL
IOSAPW
IOCKSW
IOP
IOMAX
HCKH
HCKL
HPWH
HPWL
HCKSW
HP
HMAX
TLHHS
TLHLS
THLHS
THLLS
Delays based on 35 pF loading.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
Description
Data to Pad, High Slew
Data to Pad, Low Slew
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
Input Low to High
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Asynchronous Pulse Width
Maximum Skew
Minimum Period
Maximum Frequency
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Minimum Period
Maximum Frequency
(Pad to I/O Module Input)
(Pad to S-Module Input)
(Pad to S-Module Input)
1
C C
= 4.5 V, T
(continued)
J
= 1 25° C)
Min.
4.8
4.8
3.9
9.9
4.8
4.8
9.9
‘–1’ Speed
Max.
17.3
13.1
11.6
10.9
14.4
20.2
0.06
0.11
0.04
0.05
100
100
9.2
7.7
3.5
0.9
5.5
5.5
0.9
Min.
11.6
11.6
5.7
5.7
4.4
5.7
5.7
‘Std’ Speed
Max.
10.8
20.3
15.5
14.0
12.8
16.0
22.4
0.07
0.13
0.05
0.06
9.1
4.1
1.0
6.4
6.4
1.0
85
85
Units
ns/pF
ns/pF
ns/pF
ns/pF
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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