A1240A-1CQ256B ACTEL [Actel Corporation], A1240A-1CQ256B Datasheet - Page 48

• Manufacturer Part Number: A1240A-1CQ256B
• Description: HiRel FPGAs
• Manufacturer: ACTEL [Actel Corporation]

A 32 10 0D X T i m i ng C ha r a ct er i s t i c s
(Wor st - Cas e M il it ar y Cond it ion s, V
48
Parameter
Logic Module Combinatorial Functions
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
t
t
Note:
1.
PD
PDD
RD1
RD2
RD3
RD4
RD5
RDD
CO
GO
SU
H
RO
SUENA
HENA
WCLKA
WASYN
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
Description
Internal Array Module Delay
Internal Decode Module Delay
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
Flip-Flop Clock-to-Output
Latch Gate-to-Output
Flip-Flop (Latch) Setup Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse
Width
Flip-Flop (Latch) Asynchronous Pulse
Width
1
C C
= 4.5 V, T
J
= 1 25° C)
Min.
0.5
0.0
0.9
0.0
4.3
5.6
‘–1’ Speed
Max.
3.1
3.3
1.3
1.9
2.6
3.3
0.6
0.5
3.1
3.1
3.1
Min.
0.6
0.0
1.2
0.0
5.8
7.5
‘Std’ Speed
Max.
4.1
4.3
1.8
2.6
3.4
4.3
0.8
0.6
4.1
4.1
4.1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns