A1240A-1CQ256B ACTEL [Actel Corporation], A1240A-1CQ256B Datasheet - Page 55
A1240A-1CQ256B
Manufacturer Part Number
A1240A-1CQ256B
Description
HiRel FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A1240A-1CQ256B.pdf
(98 pages)
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A 32 20 0D X T i m i ng C ha r a ct er i s t i c s
(Worst-Case Military Conditions, V
Parameter
TTL Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
d
d
t
CMOS Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
d
d
t
Notes:
1.
2.
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
LH
LCO
ACO
WDO
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
LH
LCO
ACO
WDO
TLH
THL
TLH
THL
Delays based on 35 pF loading.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
Description
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
G to Pad Low
I/O Latch Output Setup
I/O Latch Output Hold
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
G to Pad Low
I/O Latch Setup
I/O Latch Hold
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
1
1
C C
= 4.5V, T
(continued)
J
= 125°C)
Min.
0.4
0.0
0.4
0.0
‘–1’ Speed
Max.
11.5
11.5
11.5
12.3
11.5
16.3
0.04
0.06
0.05
11.5
11.5
11.5
12.3
13.7
19.2
0.06
0.05
0.05
6.6
7.1
6.6
7.1
5.1
6.3
5.1
6.3
Min.
0.5
0.0
0.5
0.0
‘Std’ Speed
Max.
15.3
15.3
15.3
16.5
15.4
21.7
0.06
0.08
0.07
15.3
15.3
15.3
16.5
18.2
25.6
0.08
0.07
0.07
8.8
9.5
8.8
9.5
6.8
8.3
6.8
8.3
H iR e l F PG A s
Units
ns/pF
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
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