nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 164

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nrf24le1-f16q48-t

Manufacturer Part Number
nrf24le1-f16q48-t
Description
Ultra-low Power Wireless System On-chip Solution
Manufacturer
ETC-unknow
Datasheet
nRF24LE1 Preliminary Product Specification
21.3.8
The ADC is interfaced to the MCU through five registers; ADCCON1 , ADCCON2 , ADCCON3 , ADCDATH and
ADCDATL . ADCCON1 , ADCCON2 and ADCCON3 contain configuration settings and status bits. The conver-
sion result is contained in the ADCDATH and ADCDATL registers.
Revision 1.1
Addr
Addr
0xD3
0xD2
Bit
Bit
5:2
1:0
7:6
4:2
SFR registers
7
6
5
Name
Name
pwrup
refsel
chsel
busy
diffm
cont
rate
RW
RW
RW
RW
RW
RW
RW
RW
R
Power-up control:
0Power down ADC
1Power up ADC and configure selected pin(s) as analog input
ADC busy flag:
0No conversion in progress
1Conversion in progress
The busy bit is cleared when a conversion result becomes avail-
able in the ADCDATH / ADCDATL registers.
Input channel select:
0000AIN0
0001AIN1
1101AIN13
11101/3 ⋅ VDD
11112/3 ⋅ VDD
Reference select:
00Internal 1.22V reference
01VDD
10External reference on AIN3
11External reference on AIN9
Selects single ended or differential mode:
00Single ended
01Differential with AIN2 as inverting input
10Differential with AIN6 as inverting input
11Not used
Selects single step or continuous conversion mode:
0Single step conversion
1Continuous conversion with sampling rate defined by rate
Selects sampling rate in continuous conversion mode:
0002 ksps
0014 ksps
0108 ksps
01116 ksps
1XXReserved
Selects power-down delay in single-step mode:
0000µs
0016µs
01024µs
011Infinite (clear pwrup to power down)
1XXReserved
:
Table 99. ADCCON1 register
164 of 191
Function
Function
Reset value: 0x00
Reset value: 0x00

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