MC2GH256NMCA-2SA00 SAMSUNG [Samsung semiconductor], MC2GH256NMCA-2SA00 Datasheet - Page 67

• Manufacturer Part Number: MC2GH256NMCA-2SA00
• Description: SAMSUNG MultiMediaCard
• Manufacturer: SAMSUNG [Samsung semiconductor]

There are five types of responses. Their formats are defined as follows:
• R1 (normal response command): code length 48 bit. The bits 45:40 indicate the index of the command to be responded
to, this value being interpreted as a binary coded number (between 0 and 63). The status of the card is coded in 32 bits.
The card status is described in Chapter
• R1b is identical to R1 with an optional busy signal transmitted on the data line DAT0. The card may become busy after
receiving these commands based on its state prior to the command reception. Refer to Section for detailed description
and timing diagrams.
• R2 (CID, CSD register): code length 136 bits. The contents of the CID register are sent as a response to the commands
CMD2 and CMD10. The contents of the CSD register are sent as a response to CMD9. Only the bits [127...1] of the CID
and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response.
• R3 (OCR register): code length 48 bits. The contents of the OCR register is sent as a response to CMD1. The level cod-
ing is as follows: restricted voltage windows=LOW, card busy=LOW.
• R4 and R5 : responses are not supported.
Revision 0.3
Width (bits)
Value
Description
Width (bits)
Value
Description
Width (bits)
Value
Description
Bit position
Bit position
Bit position
start bit
start bit
start bit
135
47
47
‘0’
‘0’
1
‘0’
1
1
transmission bit
transmission bit
transmission bit
46
134
46
‘0’
‘0’
1
‘0’
1
1
Table 6-19 : Response R1
Table 6-20 : Response R2
Table 6-21 : Response R3
command index
check bits
check bits
[133:128]
‘111111’
[45:40]
[45:40]
‘111111’
67
6
x
6
6
CID or CSD register incl. inter-
OCR register
card status
[39:8]
[39:8]
32
32
x
x
nal CRC7
[127:1]
127
x
MultiMediaCard
check bits
‘1111111’
CRC7
[7:1]
[7:1]
7
7
x
Sep.22.2005
end bit
end bit
end bit
‘1’
0
1
‘1’
‘1’
0
1
0
1
TM