MC2GH256NMCA-2SA00 SAMSUNG [Samsung semiconductor], MC2GH256NMCA-2SA00 Datasheet - Page 98

• Manufacturer Part Number: MC2GH256NMCA-2SA00
• Description: SAMSUNG MultiMediaCard
• Manufacturer: SAMSUNG [Samsung semiconductor]

In SPI mode, only the OCR, CSD and CID registers are accessible. Their format is identical to the format in the MultiMedi-
aCard mode. However, a few fields are irrelevant in SPI mode.
All timing diagrams use the following schematics and abbreviations:
All timing values are defined in Table7-9. The host must keep the clock running for at least N
the card response. This restriction applies to both command and data response tokens.
7.23.1 Command / Response
• Host Command to Card Response - Card is ready
The following timing diagram describes the basic command response (no data) SPI transaction.
CS
DataIN
DataOut
• Host Command to Card Response - card is busy
The following timing diagram describes the command response transaction for commands when the card response is of
type R1b (e.g. SET_WRITE_PROT and ERASE). When the card is signaling busy, the host may deselect it (by raising the
CS) at any time. The card will release the DataOut line one clock after the CS going high. To check if the card is still busy,
it needs to be reselected by asserting (set to low) the CS signal. The card will resume busy signal (pulling DataOut low)
one clock after the falling edge of CS.
7.22 Card Registers
7.23 SPI Bus Timing Diagrams
Revision 0.3
Data block
Command
Response
H H L L L
X X
Z Z Z H H H H
Symbol
Busy
H
X
L
Z
*
←⎯ N
H * * H
Figure 7-15 : SPI Command/Response Transaction, Card Is Ready
CS
→
Signal is high (logical ‘1’
Signal is low (logical ‘0’)
Don’t care (Undefined Value)
High impedance state (-> = 1)
Repeater
Busy Token
Command token
Response token
Data token
6 Bytes Command
* * * * * * * * *
* * * * * * * * * * * * * * * * * * * *
H H * * * H
98
←⎯ N
H H H H H
CR
→
Definition
1 or 2 Bytes Response
* * * * * * * * *
CR
clock cycles after receiving
MultiMediaCard
←⎯ N
H H H H H Z Z
L L L L H H H
H * * H
Sep.22.2005
EC
→
X X X
TM