EPF10K10 ETC, EPF10K10 Datasheet - Page 60

• Manufacturer Part Number: EPF10K10
• Description: EMBEDDED PROGRAMMABLE LOGIC FAMILY
• Manufacturer: ETC

60
FLEX 10K Embedded Programmable Logic Family Data Sheet
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SAMELAB
SAMEROW
SAMECOLUMN
DIFFROW
TWOROWS
LEPERIPH
LABCARRY
LABCASC
DIN2IOE
DIN2LE
DCLK2IOE
DCLK2LE
DIN2DATA
DRR
INSU
INH
OUTCO
Table 36. Interconnect Timing Microparameters
Table 37. External Reference Timing Parameters
Table 38. External Timing Parameters
Symbol
Symbol
Symbol
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
Routing delay for an LE driving an IOE in the same column
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Delay from dedicated input pin to IOE control input
Delay from dedicated input pin to LE or EAB control input
Delay from dedicated clock pin to IOE clock
Delay from dedicated clock pin to LE or EAB clock
Delay from dedicated input or clock to LE or EAB data
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Note (10)
Parameter
Parameter
Parameter
Note (8)
Note (1)
Altera Corporation
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(9)
Conditions
Conditions
Conditions