EPF10K10 ETC, EPF10K10 Datasheet - Page 61

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EPF10K10

Manufacturer Part Number
EPF10K10
Description
EMBEDDED PROGRAMMABLE LOGIC FAMILY
Manufacturer
ETC
Datasheet

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Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) These timing parameters are sample-tested only.
t
t
t
t
t
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Table 39. External Bidirectional Timing Parameters
Symbol
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
Operating conditions: V
Operating conditions: V
Operating conditions: V
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
Contact Altera Applications for test circuit specifications and test conditions.
Setup time for bidirectional pins with global clock at adjacent LE register
Hold time for bidirectional pins with global clock at adjacent LE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate = off
V
V
V
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 5.0 V 5% for commercial use in FLEX 10K devices.
= 5.0 V 10% for industrial use in FLEX 10K devices.
= 3.3 V 10% for commercial or industrial use in FLEX 10KA devices.
= 3.3 V 10% for commercial or industrial use in FLEX 10K devices.
= 2.5 V 0.2 V for commercial or industrial use in FLEX 10KA devices.
= 2.5 V, 3.3 V, or 5.0 V.
FLEX 10K Embedded Programmable Logic Family Data Sheet
Parameter
Note (10)
Condition
61

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