Z80181 Zilog., Z80181 Datasheet
Z80181
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Z80181 Summary of contents
Page 1
... Clock Generator One Channel of Z85C30 Serial Communication Controller (SCC) GENERAL DESCRIPTION ™ The Z80181 SAC Smart Access Controller (hereinafter, referred to as Z181 SAC sophisticated 8-bit CMOS microprocessor that combines a Z180-compatible MPU (Z181 MPU), one channel of Z85C30 Serial Communica- tion Controller (SCC), a Z80 CTC, two 8-bit general-pur- ...
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... Zilog GENERAL DESCRIPTION (Continued) D7-D0 Z80180 Compatible Control A19-A0 Logic A19-A12 Address Decode /ROMCS Logic /RAMCS Z80181 = Z180 + SCC/2 + CTC + PIA 2-2 (1 Channel) Core Glue Figure 1. Z80181 Functional Block Diagram MART CCESS ONTROLLER Tx Data SCC Rx Data Modem/Control 8 Signals CTC PIA1 Bit Programmable ...
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... MART CCESS ONTROLLER 85 80 /TEND1 /DREQ1 CKS RxS//CTS1 TxS 75 CKA1//TEND0 RxA1 TEST TxA1 CKA0//DREQ0 70 RxA0 TxA0 /DCD0 /CTS0 /RTS0 65 A18/TOUT A19 GND IEI /ROMCS 60 IEO GND /DCD /CTS /RTS 55 /DTR//REQ TxD /TRxC RxD /W//REQ 50 Z80181 ™ SAC 2-3 ...
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... Machine cycle. This signal is analogous to the /LIR signal of the Z64180. The Refresh Signal. When the dynamic memory refresh address is on the low order 8-bits of the address bus (A7 - A0), /RFSH is active along with the /MREQ signal. This signal is analogous to the /REF signal of the Z64180. Z80181 ™ SAC CCESS ...
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... Wait Signal. /WAIT informs the CPU that the specified memory or peripheral is not ready for a data transfer. As long as /WAIT signal is active, the MPU is continuously kept in the wait state. Internally, the /WAIT signal from the SCC interface logic is connected to this line, and requires an external pull-up resistor. Z80181 ™ SAC CCESS ...
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... CSI/O Tx Data. This line carries the transmit data from the CSIO channel. DMAC1 Request. This pin is used to request a DMA transfer from DMA channel 1. DMA1 monitors this input to determine when an external device is ready for a read or write operation. Z80181 ™ SAC CCESS ...
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... Also, it can supply the output of the Digital Phase-Locked Loop, the crystal oscillator, the Baud Rate Generator, or the transmit clock in the output mode. Z80181 ™ SAC ...
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... Data Carrier Detect. This pin functions as receiver enable programmed for auto enable. Otherwise, it may be used as a general-purpose input. This input is Schmitt- trigger buffered to accommodate slow rise-time inputs. The SCC detects pulses on this input and can interrupt the CPU on both logic level transitions. Z80181 ™ SAC CCESS ...
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... It is program selectable whether the active edge is rising or falling. On reset, these signals are set to PIA13-10 as inputs. Port 2 Data. These lines are configured as inputs or outputs on a bit-by-bit basis. On reset, they are inputs. Z80181 ™ SAC ...
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... CPU Operation (1st Opcode fetch CPU Operation (2nd and 3rd Opcode fetch CPU Operation (MC other than Opcode fetch DMA operation HALT mode SLEEP mode (Incl. System STOP mode) Z80181 ™ SAC CCESS ONTROLLER DS971800500 ...
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... Crystal oscillator connecting terminal. System Clock. Single-phase clock output from Z181 MPU. Enable Clock. Synchronous Machine cycle clock output during a bus transaction. Test pin. Used in the open state. Power Supply. +5 Volts Power Supply. 0 Volts Z80181 ™ SAC CCESS ONTROLLER 2-11 ...
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... The following subsections describe each individual functional unit of the SAC. Bus State Control CPU DMACs (2) Asynchronous SCI (Channel 0) Asynchronous SCI (Channel 1) D7-D0 Figure 3. Z181 MPU Block Diagram Z80181 ™ SAC MART CCESS ONTROLLER Interrupt /DREQ1 /TEND TxA0 CKA0 /DREQ0 ...
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... To ease interfacing with slow memory and I/O devices, the Z181 MPU unit has a programmable wait state generator. By programming the DMA/WAIT Control Register (DCNTL three wait states are automatically inserted in mem- ory and I/O cycles. This unit also inserts wait states during on-chip DMA transactions. Z80181 ™ SAC CCESS ...
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... CPU for a broad range of counting and timing applications. Typical applications include event counting, interrupt and interval counting, and serial baud rate clock generation MART CCESS ONTROLLER } Serial Data Channel } Channel Clocks /SYNC /Wait Discrete Modem, DMA, Control or Other & Status Controls DS971800500 Z80181 ™ SAC ...
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... Internal Control Logic Interrupt Logic I/O Counter/ Timer Logic /RESET Figure 5. CTC Block Diagram XTAL Crystal Inputs EXTAL Figure 6. Circuit Configuration For Crystal MART CCESS ONTROLLER /INT IEI IEO 4 ZC/TO Mutiplexed 4 with PIA1 CLK/TRG C1 C2 Z80181 ™ SAC 2-15 ...
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... SAC’s system control. The SAC’s I/O addresses are listed in Table 1. These registers are assigned in the SAC’s I/O addressing space and the I/O addresses are fully de- coded from A7-A0 and have no image. Z80181 ™ SAC ...
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... The /IOC bit (Bit D5) of this register is pro- grammed that the timing of the /RD and /IORQ signals are compatible with Z80 peripherals. For detailed information, refer to the Z180 Technical Manual. Z80181 ™ SAC ...
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... ONTROLLER MODE Selection Read - Multiprocessor Bit Receive Write - Error Flag Reset Request To Send Transmit Enable Receive Enable Multiprocessor Enable MODE Selection Read - Multiprocessor Bit Receive Write - Error Flag Reset CKA1 Disable Transmit Enable Receive Enable Multiprocessor Enable DS971800500 Z80181 ™ SAC ...
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... Clock Source and Speed Select Divide Ratio Parity Even or Odd Clear To Send/Prescale Multiprocessor Multiprocessor Bit Transmit (x64) 480 Ø 1920 960 Ø 3840 1920 Ø 7680 3840 Ø 15360 7680 Ø 30720 15360 Ø 61440 30720 Ø 122880 Z80181 ™ SAC 2-19 ...
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... Multiprocessor Bit Transmit (Divide Ratio = 30 (x16 (x64) Ø 480 Ø 1920 Ø 960 Ø 3840 Ø 1920 Ø 7680 Ø 3840 Ø 15360 Ø 7680 Ø 30720 Ø 15360 Ø 61440 Ø 30720 Ø 122880 DS971800500 Z80181 ™ SAC ONTROLLER ...
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... Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full TIE 0 Transmit Interrupt Enable Transmit Data Register Empty /CTS1 Enable Receive Interrupt Enable Framing Error Parity Error Over Run Error Receive Data Register Full Z80181 ™ SAC ONTROLLER 2-21 ...
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... Figure 17. CSI/O Control Register MART CCESS ONTROLLER Addr 08h Received Data Addr 09h Received Data Addr 0Ah SS0 1 R/W Speed Select Transmit Enable Receive Enable End Interrupt Enable End Flag Baud Rate 320 640 1280 20) DS971800500 Z80181 ™ SAC ...
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... When Read, read Data Register L before reading Data Register H. Figure 21. Timer 0 Data Register H TMDR1H Read/Write Addr 15h When Read, read Data Register L before reading Data Register H. Figure 22. Timer 1 Data Register H RLDR1L Read/Write Addr 16h Z80181 ™ SAC 2-23 ...
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... FRC Read Only Addr 18h Figure 28. Free Running Counter MART CCESS ONTROLLER RLDR1H Read/Write Addr 17h Timer Down Count Enable 1,0 Timer Output Control 1,0 Timer Interrupt Enable 1,0 Timer Interrupt Flag 1,0 0 DS971800500 Z80181 ™ SAC ...
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... Bits 0-2 (3) are used for DAR0B A19, A18, A17, A16 DMA Transfer Request /DREQ0 (external RDR0 (ASCI0 TDR0 (ASCI1 Not Used Figure 30. DMA 0 Destination Address Registers Z80181 ™ SAC CCESS ONTROLLER 2-25 ...
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... Figure 33. DMA 1 I/O Address Registers MA0 MA8 Figure 34. DMA 1 Byte Count Registers MA16 MART CCESS ONTROLLER IAR1L Read/Write Addr 2Bh IA7 IA0 IAR1H Read/Write Addr 2Ch IA15 IA8 BCR1L Read/Write Addr 2Eh BC7 BC0 BCR1H Read/Write Addr 2Fh BC15 BC8 DS971800500 Z80181 ™ SAC ...
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... R DMA Master Enable DMA Interrupt Enable 1, 0 DMA Enable Bit Write Enable 1, 0 DMA Enable Memory MODE Select Ch 0 Source Mode Destination Mode 1, 0 Source Address M SAR0+1 M SAR0-1 M SAR0 Fixed I/O SAR0 Fixed Z80181 ™ SAC ONTROLLER 2-27 ...
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... Address Increment/Decrement M - I/O MAR1+1 IAR1 Fixed M - I/O MAR1-1 IAR1 Fixed I IAR1 Fixed MAR1+1 I IAR1 Fixed MAR1-1 Figure 37. DMA/WAIT Control Register MART CCESS ONTROLLER DIM0 0 R/W DMA Ch 1 I/O Memory Mode Select /DREQi Select I/0 Wait Insertion Memory Wait Insertion DS971800500 Z80181 ™ SAC ...
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... Figure 39. MMU Bank Base Register Addr 3Ah CA1 CA0 BA3 BA2 BA1 R/W R/W R/W R/W R MART CCESS ONTROLLER Addr 38h CB0 0 R/W MMU Common Base Register Addr 39h BB0 0 R/W MMU Bank Base Register BA0 0 R/W MMU Bank Area Register MMU Common Area Register Z80181 ™ SAC 2-29 ...
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... Interval of Refresh Cycle 10 states 20 states 40 states 80 states Figure 43. Refresh Control Register MART CCESS ONTROLLER Addr 33h - 0 Interrupt Vector Low Addr 34h ITE0 1 R/W /INT Enable Undefined Fetch Object TRAP Addr 36h 0 R/W Cycle Select Refresh Wait State Refresh Enable DS971800500 Z80181 ™ SAC ...
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... IOA6 Upon Reset 0 R/W R/W R/W DS971800500 /IOC - - - R/W Figure 44. Operation Mode Control Register IOSTP - - - R/W Figure 45. I/O Control Register MART CCESS Addr 3Eh - - 1 1 I/O Compatibility /M1 Temporary Enable /M1 Enable Addr 3Fh - - 1 1 I/O Stop I/O Address Combination reserved Z80181 ™ SAC ONTROLLER 2-31 ...
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... Automatic Trigger When Time Constant is Loaded 1 CLK/TRG Pulse Starts Timer CLK/TRG Edge Selection 0 Selects Falling Edge 1 Selects Rising Edge Prescaler Value * 1 Value of 256 0 Value of 16 Mode 0 Selects Timer Mode 1 Selects Counter Mode Interrupt 1 Enables Interrupt 0 Disables Interrupt DS971800500 Z80181 ™ SAC ...
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... RR8 Receive buffer. RR10 Miscellaneous status bits. RR12 Lower byte of baud rate. RR13 Upper byte of baud rate generator time constant. RR15 External Status interrupt information. Z80181 ™ SAC MART CCESS ONTROLLER Addr: E4h 0 Interrupt Vector Word 1 Control Word ...
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... Modified if VIS bit in Write register 9 is set. Read Register All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC/Framing Error End of Frame (SDLC) Figure 49. SCC Read Register Bit Functions Z80181 ™ SAC MART CCESS ONTROLLER ...
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... BC6 BC7 Read Register BC8 BC9 BC10 BC11 BC12 BC13 FDA: FIFO Available Status 1 Status Reads from FIFO FOS: FIFO Overflow Status 1 FIFO Overflowed 0 Normal Z80181 ™ SAC MART CCESS ONTROLLER 0 On Loop 0 0 Loop Sending 0 ...
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... WR10 Miscellaneous transmit and receive control bits WR11 Clock mode controls for receive and transmit WR12 Lower byte of baud rate generator WR13 Upper byte of baud rate generator WR14 Miscellaneous control bits WR15 External status interrupt enable control Z80181 ™ SAC ...
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... Parity is Special Condition Int Disable Int On First Character or Special Condition 1 0 Int On All Rx Characters or Special Condition Int On Special Condition Only WAIT/DMA Request On Receive//Transmit /WAIT/DMA Request Function WAIT/DMA Request Enable ( Interrupt Vector (c) Z80181 ™ SAC 2-37 ...
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... Write Register Parity Enable Parity EVEN//ODD MART CCESS ONTROLLER Tx CRC Enable RTS /SDLC/CRC-16 Tx Enable Send Break Tx 5 Bits(Or Less)/Character Tx 7 Bits/Character Tx 6 Bits/Character Tx 8 Bits/Character DTR (f) DS971800500 Z80181 ™ SAC ...
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... Sync7 Sync6 Sync5 ( MART CCESS ONTROLLER Sync0 Monosync, 8 Bits Sync0 Monosync, 6 Bits Sync0 Bisync, 16 Bits 1 Bisync, 12 Bits ADR0 SDLC x SDLC (Address Range) Sync0 Monosync, 8 Bits x Monosync, 6 Bits Sync8 Bisync, 16 Bits Sync4 Bisync, 12 Bits 0 SDLC Z80181 ™ SAC 2-39 ...
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... Out - DPLL Output /TRxC O/I 0 Transmit Clock - /RTxC Pin 1 Transmit Clock - /TRxC Pin 0 Transmit Clock - BR Generator Output 1 Transmit Clock - DPLL Output /RTxC Xtal//No Xtal (k) TC0 TC1 TC2 TC3 Lower Byte of Time Constant TC4 TC5 TC6 TC7 (l) DS971800500 Z80181 ™ SAC ...
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... Function Auto Echo Local Loopback Null Command Enter Search Mode Reset Missing Clock Disable DPLL Set Source = BR Generator Set Source = /RTxC Set FM Mode Set NRZI Mode (n) 0 Zero Count IE SDLC FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE Z80181 ™ SAC 2-41 ...
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... MART CCESS ONTROLLER Input 0 - Output 1 - Input 0 - Output 1 - Input 0 - Output 1 - Input 0 - Output 1 - Input 0 - Output 1 - Input 0 - Output 1 - Input 0 - Output 1 - Input 0 - Output PIA 2 I/O Data DS971800500 Z80181 ™ SAC ...
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... RAMLBR registers are re-initialized to lower values. EBH 7 6 A12 A13 A14 A15 A16 A17 A18 A19 Figure 56. RAM Lower Boundary Register MART CCESS ONTROLLER A19-A12 0 A19-A12 > (RAMLBR A12 A13 A14 A15 A16 A17 A18 A19 Z80181 ™ SAC ”. OUT 2-43 ...
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... Reserved - Program as 0 Disable /ROMCS 1 /ROMCS is Disabled 0 /ROMCS is Enabled Daisy Chain Configuration 1 IEI Pin-CTC-SCC-IEO Pin 0 IEI Pin-SCC-CTC-IEO Pin Reserved - Program as 0 Figure 58. System Configuration Register MART CCESS ONTROLLER A12 A13 A14 A15 A16 A17 A18 A19 DS971800500 Z80181 ™ SAC ...
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... Z181 is in “ROM emulator mode”. In this mode, bus direction for certain transaction periods are set to the opposite direction to export internal bus transactions out- side the Z80181. This allows the use of ROM emulators/ logic analyzers for applications development. This bit’s default (after Reset ...
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... Z80181 Data Bus Out Out (REME Bit = 1) Interrupt Acknowledge Transaction Intack For Intack For On-Chip Off-Chip Peripheral Peripheral (SCC/CTC) Z80181 Data Bus Z In (REME Bit = 0) Z80181 Data Bus Out In (REME Bit = 1) 2-46 I/O I/O Write Write To Read From To Off-Chip Off-Chip Memory Out In Out Out ...
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... Zilog Table 5 shows the state of the SAC’s data bus when the Z80181 is NOT in bus master condition. Table 5. Data Bus Direction for External Bus Master (Z80181 Is Not Bus Master) I/O And Memory Transactions I/O I/O Write To Read From On-Chip On-Chip Peripherals Peripherals Peripheral Peripheral ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. From Output Under Test Vcc + 5.50V Figure 59. Standard Test Circuit MART CCESS ONTROLLER +5V 2.1 K 100 pf 250 A DS971800500 Z80181 ™ SAC ...
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... Max = 0.8V (all output terminals are at no load 5.0V CC DS971800500 Min Typ Max V –0 2.0 V +0.3 CC –0.3 0.6 –0.3 0.8 2.4 V –1 Z80181 SAC MART CCESS ONTROLLER Unit Condition -200 – 2 0.5 – V –0 0.5 – V –0 ...
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... Address /ROMCS /RAMCS /WAIT /MREQ /RD / "H" /IORQ /WR Data In 61 /RESET 67 2- Figure 60a. Opcode Fetch Cycle MART CCESS ONTROLLER DS971800500 Z80181 ™ SAC ...
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... Memory Read/Write cycle timing is the same as this figure, except there is no automatic wait status (Twa), and /MREQ is active instead of /IORQ. Figure 60b. I/O Read/Write, Memory Read/Write Timing DS971800500 T2 Twa 25, 25a MART CCESS ONTROLLER [1] Z80181 ™ SAC 2-51 ...
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... Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode HALT Mode, SLEEP Mode, SYSTEM STOP Mode) 2- [3] [3] Output buffer is off at this point [4] Refer to Table C, parameter 7 Figure 61. CPU Timing MART CCESS ONTROLLER DS971800500 Z80181 ™ SAC ...
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... Zilog I/O Read Cycle T1 T2 Ø Address 27 /IORQ 9 /RD /WR DS971800500 I/O Write Cycle Figure 62. CPU Timing (/IOC = 0) (I/O Read Cycle, I/O Write Cycle MART CCESS ONTROLLER Z80181 ™ SAC 2-53 ...
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... DMA cycle starts. [4] CPU cycle starts. 2-54 CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi [ [3] 17 Figure 63. DMA Control Signals MART CCESS ONTROLLER [4] 47 DS971800500 Z80181 ™ SAC ...
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... BUS RELEASE Mode E SLEEP Mode SYSTEM STOP Mode (BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode) DS971800500 (a) E Clock Timing 48 (b) E Clock Timing Figure 64. E Clock Timing MART CCESS ONTROLLER Z80181 ™ SAC 2-55 ...
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... Z180 MPU Timing T2 Ø E (Example: I/O Read - Op-code Fetch) E (I/O Write) Ø A18/TOUT 2- Figure 65. E Clock Timing (Minimum timing example of PWEL and PWEH) Timer Data Reg = 0000H 54 Figure 66. Timer Output Timing MART CCESS ONTROLLER DS971800500 Z80181 ™ SAC ...
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... Zilog SLP Instruction Fetch T3 Ø /INTi /NMI A18-A0 /MREQ, /M1 /RD /HALT DS971800500 Figure 67. SLP Execution Cycle MART CCESS ONTROLLER Next Op-code Fetch Z80181 ™ SAC 2-57 ...
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... Figure 68. CSI/O Receive/Transmit Timing Table A. Z180 CPU & 180 Peripherals Timing MART CCESS ONTROLLER tcyc 57 58 11.5 tcyc 16.5 tcyc 59 60 Z8018110 Min Max Unit 100 2000 DS971800500 Z80181 ™ SAC ...
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... Clock Rise to /HALT Rise Delay 44 tDRQS /DREQi Setup Time to Clock Rise 45 tDRQH /DREQi Hold Time from Clock Rise 46 tTED1 Clock Fall to /TENDi Fall Delay DS971800500 Z80181 SAC MART CCESS ONTROLLER Z8018110 Min Max Unit ...
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... Fall Time 68 tIr Input Rise Time (Except EXTAL, /RESET) 69 tIf Input Fall Time (Except EXTAL, /RESET) 70 TdCS(A) Address Valid to /ROMCS, /RAMCS Valid Delay 2-60 Z80181 SAC MART CCESS ONTROLLER Z8018110 Min Max Unit 110 150 ns 150 ns 7 ...
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... Figure 69. CTC Timing Table B. CTC Timing Parameters Min 90 (2TcC MART CCESS ONTROLLER Z8018110 Max Unit Note (TcC+100) ns [B1] ns [B2 [B1] (1)+(3) ns [B2] TcC+(1)+(3) ns [B2 [B3 Z80181 ™ SAC 2-61 ...
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... TdPC(INT) Clock to /INT Valid Delay 7 TdRDA(INT) /M1 Fall to /INT Inactive Delay Note for Table C: [C1] Open-drain output, measured with open-drain test load. 2- Figure 70. SCC AC Parameters Z8018110 Min Z80181 SAC MART CCESS ONTROLLER 5 Max Unit Note 180 + TcC ns [C1] 180 ...
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... Receive 3 RxD 7 /SYNC External /TRxC, /RTxC Transmit TxD /TRxC Output /RTxC /TRxC /CTS, /DCD /SYNC Input DS971800500 15 18 Figure 71. SCC General Timing MART CCESS ONTROLLER Z80181 ™ SAC 2-63 ...
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... A C MART CCESS ONTROLLER Z8018110 Min Max Unit 200 ns 300 125 125 ns –150 ns 5TcC ns 150 ns 150 ns 140 ns 120 ns 120 ns 400 ns 100 1000 ns 120 ns 120 ns 400 ns 120 ns 100 DS971800500 Z80181 ™ SAC Note [D1] [D1] [D1,4] [D1,4] [D1] [D1] [D2] [D2,4] [D5] [D5] [D5,6] [D3] [D5] [D5] [D5,7] [D6,7] ...
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... Receive /W//REQ Request /W//REQ Wait /SYNC Output /INT /RTxC, /TRxC Transmit /W//REQ Request /W//REQ Wait /DTR//REQ Request /INT /CTS, /DCD /SYNC Input /INT DS971800500 Figure 72. SCC System Timing Z80181 ™ SAC MART CCESS ONTROLLER 2-65 ...
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... Table E. SCC System Timing Parameters MART CCESS ONTROLLER Z8018110 Min Max Unit 8 12 TcC 8 14 TcC 4 7 TcC 10 16 TcC 5 8 TcC 5 11 TcC 4 7 TcC 6 10 TcC 2 6 TcC 2 6 TcC DS971800500 Z80181 ™ SAC Note [E2] [E1,2] [E2] [E1,2] [E3] [E1,3] [E3] [E1,3] [E1] [E1] ...
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... PIA Output Table F. PIA General-Purpose I/O Timing Parameters No Symbol Parameter 1 TsPIA(C) PIA Data Setup time to Clock Rise 2 TdCr(PIA) Clock Rise to PIA Data Valid Delay DS971800500 Figure 73. PIA Timing MART CCESS ONTROLLER Z8018110 Min Max Unit Z80181 ™ SAC 2-67 ...
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... IEI Fall to IEO Fall Delay IEO Rise to IEO Rise Delay /M1 Fall to IEO Fall Delay Clock Rise to /WAIT Fall Delay Clock Rise to /WAIT Rise Delay MART CCESS ONTROLLER Z8018110 Min Max Unit 20 ns 2TcC DS971800500 Z80181 ™ SAC ...
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... If any peripheral is connected externally with a lower daisy chain priority than Z181 peripherals, /IORQ must be de- layed by external logic as shown in Figure 79. IEO IEI IEO IEI CTC Z80181 Z80181 MART CCESS ONTROLLER ), the external daisy-chain device WA IEO SCC ™ ...
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... Data in to /WR Fall Setup Time /IORQ, /WR Rise to Data In Hold Time Address to /IORQ Fall Setup Time Address to /RD Fall Setup Time Address to /WR Fall Setup Time Z80181 SAC MART CCESS ONTROLLER Z8018110 Min Max Unit 120 ...
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... Valid Access Recovery Time 2 TdRDr(REQ) /RD Rise to /DTR//REQ Not Valid Delay Note for Table I: [1] Only applies between transactions involving the SCC. DS971800500 1 Figure 77. SCC External BUS Master Timing MART CCESS ONTROLLER 2 Z8018110 Min Max Unit 4TcC ns 4TcC ns Z80181 ™ SAC Notes [1] 2-71 ...
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... Settle Time for Off-chip Z80 On-chip CTC Peripherals Settle Time for SCC /WAIT Signal generated by interface circuit IEO IEI IEO SCC /IORQ Z80181 MART CCESS ONTROLLER Peripheral IEI IEO Device(s) External Logic to Extend /IORQ Signal DS971800500 Z80181 ™ SAC ...
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... Zilog PACKAGE INFORMATION DS971800500 100-Pin QFP Package Diagram Z80181 ™ SAC MART CCESS ONTROLLER 2-73 ...
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... E = – +100 C Environmental C = Plastic Standard Speed MHz Example: Z 80181 Z80181, 10 MHz, QFP, – +100 C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc ...