Z80181 Zilog., Z80181 Datasheet - Page 5

• Manufacturer Part Number: Z80181
• Description: SMART ACCESS CONTROLLER (SAC)
• Manufacturer: Zilog.

Zilog
Pin Name
/INT0
/INT1,
/INT2
/NMI
/HALT
/BUSREQ
/BUSACK
/WAIT
DS971800500
Pin Number
100
1, 2,
99
81
97
96
95
Input/Output, Tri-State
Wired-OR I/O, Active 0
In, Active 0
In, Active 0
Out, tri-state, Active 0
In, Active 0
Out, Active 0
Wired-OR I/O, Active 0
Function
Maskable Interrupt Request 0. Interrupt is generated by
peripheral devices. This signal is accepted if the interrupt
enable Flip-Flop (IFF) is set to “1”. Internally, the SCC and
CTC’s interrupt signals are connected to this line, and
require an external pull-up resistor.
Maskable Interrupt Request 1 and 2. This signal is
generated by external peripheral devices. The CPU hon-
ors these requests at the end of current instruction cycle as
long as the /NMI, /BUSREQ and /INT0 signals are inactive.
The CPU will acknowledge these interrupt requests with an
interrupt acknowledge cycle. Unlike the acknowledgment
for /INT0, during this cycle, neither /M1 or /IORQ will
become active.
Non-Maskable Interrupt Request Signal. This interrupt
request has a higher priority than the maskable interrupt
request and does not rely upon the state of the interrupt
enable Flip-Flop (IFF).
Halt Signal. This signal is asserted after the CPU has
executed either the HALT or SLP instruction, and is waiting
for either non-maskable interrupt maskable interrupt be-
fore operation can resume. It is also used with the /M1 and
ST signals to decode the status of the CPU machine cycle.
BUS Request Signal. This signal is used by external
devices (such as a DMA controller) to request access to
the system bus. This request has higher priority than /NMI
and is always recognized at the end of the current machine
cycle. This signal will stop the CPU from executing further
instructions and place the address bus, data bus, /MREQ,
/IORQ, /RD and /WR signals into the high impedance state.
/BUSREQ is normally wired-OR and a pull-up resistor is
externally connected.
Bus Acknowledge Signal. In response to /BUSREQ sig-
nal, /BUSACK informs a peripheral device that the address
bus, data bus, /MREQ, /IORQ, /RD and /WR signals have
been placed in the high impedance state.
Wait Signal. /WAIT informs the CPU that the specified
memory or peripheral is not ready for a data transfer. As
long as /WAIT signal is active, the MPU is continuously kept
in the wait state. Internally, the /WAIT signal from the SCC
interface logic is connected to this line, and requires an
external pull-up resistor.
S
MART
A
CCESS
C
ONTROLLER
Z80181
SAC
2-5
™