Z80181 Zilog., Z80181 Datasheet - Page 20

• Manufacturer Part Number: Z80181
• Description: SMART ACCESS CONTROLLER (SAC)
• Manufacturer: Zilog.

Zilog
ASCI CHANNELS CONTROL REGISTERS (Continued)
General
Divide Ratio
SS, 2, 1, 0
000
001
010
011
100
101
110
111
2-20
Upon Reset
R/W
Bit
PS = 0
(Divide Ratio = 10)
DR = 0 (x16)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
External Clock (Frequency < Ø
CNTLB1
Invalid
MPBT
R/W
160
320
640
1280
2560
5120
10240
R/W
MP
0
/CTS/
R/W
PS
0
Figure 10. ASCI Control Register B (Ch. 1)
PE0
R/W
0
DR = 1 (x64)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
R/W
DR
640
1280
2580
5120
10240
20480
40960
0
40)
SS2
R/W
1
SS1
R/W
1
Addr 03h
SS0
R/W
1
PS = 1
(Divide Ratio = 30)
DR = 0 (x16)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
480
960
1920
3840
7680
15360
30720
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Read - Status of /CTS pin
Write - Select PS
Multiprocessor
Multiprocessor Bit Transmit
S
MART
DR = 1 (x64)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
A
CCESS
1920
3840
7680
15360
30720
61440
122880
C
DS971800500
ONTROLLER
Z80181
SAC
™