PCF8811MU/2DA/1 PHILIPS [NXP Semiconductors], PCF8811MU/2DA/1 Datasheet - Page 24

• Manufacturer Part Number: PCF8811MU/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 4 Co and D/C definition
A read sequence is given in Fig.29 and again this
sequence follows after the Hs-mode is selected. The
PCF8811 will immediately start to output the requested
data until a not-acknowledge is transmitted by the master.
Before the read access, the user has to set the D/C bit to
the appropriate value by a preceding write access. The
write access should be terminated by a RE-START
condition so that the Hs-mode is not disabled.
After the last control byte, depending on the D/C bit
setting, either a series of display data bytes or command
data bytes may follow. If the D/C bit was set to logic 1,
these display bytes are stored in the display RAM at the
address specified by the data pointer.
2004 May 17
handbook, full pagewidth
Co
D/C
80
BIT
128 pixels matrix LCD driver
LOGIC
LEVEL
0
1
0
1
S
R/W
N/A
MASTER CODE
0
1
0
1
F/S-mode
last control byte to be sent; only a stream of data bytes are allowed to follow; this stream
may only be terminated by a STOP or RE-START condition
another control byte will follow the data byte unless a STOP or RE-START condition is
received
data byte will be decoded and used to set-up the device
data byte will return the status byte
data byte will be stored in the display RAM
RAM read back is not supported
A
Fig.26 Data transfer format in Hs-mode.
Sr SLAVE ADD.
Hs-mode (current-source for SCLH enabled)
R/W
24
The data pointer is automatically updated and the data is
directed to the intended PCF8811 device. If the D/C bit of
the last control byte was set to logic 0, these command
bytes will be decoded and the setting of the device will be
changed according to the received commands. The
acknowledgement after each byte is made only by the
addressed PCF8811. At the end of the transmission the
I
back to the F/S-mode, however, to reduce the overhead of
the master code, it is possible that a master can link
a number of Hs-mode transfers, separated by repeated
START conditions (Sr).
A
2
C-bus master issues a STOP condition (P) and switches
(n bytes
ACTION
DATA
ack.)
A/A
Sr SLAVE ADD.
P
Hs-mode continues
F/S-mode
MSC616
Product specification
PCF8811