DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 25

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

Clock Control (CKCON)
SFR 8Eh
WD1, WD0
Bits 7-6
T2M
Bit 5
T1M
Bit 4
T0M
Bit 3
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
RW-0
WD1
7
Watchdog Timer Mode Select 1-0. These bits determine the watchdog timer
time-out period. The timer divides the crystal frequency by a programmable
value as shown below. The divider value is expressed in clock (crystal) cycles.
The use of PMM1 or PMM2 will further divide the clock cycle count by either
16 or 256, respectively. Note that the reset time-out is 512 clocks longer than
the interrupt, regardless of whether the interrupt is enabled.
WD1
Timer 2 Clock Select. This bit controls the division of the system clock that
drives Timer 2. This bit has no effect when the timer is in baud rate generator or
clock output modes. Clearing this bit to 0 maintains 80C32 compatibility. This
bit has no effect on instruction cycle timing.
0 = Timer 2 uses a divide by 12 of the crystal frequency.
1 = Timer 2 uses a divide by 4 of the crystal frequency.
Timer 1 Clock Select. This bit controls the division of the system clock that
drives Timer 1. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 1 uses a divide by 12 of the crystal frequency.
1 = Timer 1 uses a divide by 4 of the crystal frequency.
Timer 0 Clock Select. This bit controls the division of the system clock that
drives Timer 0. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 0 uses a divide by 12 of the crystal frequency.
1 = Timer 0 uses a divide by 4 of the crystal frequency.
0
0
1
1
RW-0
WD0
6
WD0
0
1
0
1
RW-0
T2M
5
Interrupt Divider
2
2
2
2
17
20
23
26
25 of 175
RW-0
T1M
4
RW-0
T0M
3
Reset Divider
2
2
2
2
17
20
23
26
High-Speed Microcontroller User’s Guide
+ 512
+ 512
+ 512
+ 512
RW-0
MD2
2
RW-0
MD1
1
RW-1
MD0
0