DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 98
DS80C320-ECD
Manufacturer Part Number
DS80C320-ECD
Description
High-Speed Microcontroller User Guide
Manufacturer
DALLAS [Dallas Semiconductor]
Datasheet
1.DS80C320-ECD.pdf
(175 pages)
- Current page: 98 of 175
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In addition, the DS87C520 and DS87C530 has the capability to operate from the internal ring oscillator
during normal operation, not only during the crystal warm-up period. Table 7-3 summarizes the new
control bits associated with the power management features.
POWER MANAGEMENT AND STATUS BIT SUMMARY Table 7-3
POWER MANAGEMENT MODE TIMING
The two power management modes reduce power consumption by internally dividing the clock signal to
the device, causing it to operate at a reduced speed. When PMM is invoked, the external crystal will
continue to operate at full speed. The difference is that the device uses 16 (PMM1) or 256 (PMM2)
external clocks to generate each internal clock cycle (C1, C2, C3 or C4) as opposed to 1 clock per internal
clock cycle in divide by 4 mode. This translates to 64 or 1024 external clocks per machine cycle in
PMM1 or PMM2, respectively. Relative timing relationships of all signals when the device is operating
in PMM1 or PMM2 will remain the same as the 4 cycle timing. Note that all internal functions, on-board
timers (including serial port baud rate generation), watchdog timer, and software timing loops will also
run at the reduced speed. Most applications will not find it necessary to attend to this much detail, but the
information is provided for calculating critical timings. Figure 7-2 demonstrates the internal timing
relationships during PMM1.
BIT NAME
CD1, CD0
SWB
PIP
HIP
LIP
SPTA1
SPRA1
SPTA0
SPRA0
LOCATION
PMR.7–6
PMR.5
STATUS.7
STATUS.6
STATUS.5
STATUS.3
STATUS.2
STATUS.1
STATUS.0
FUNCTION
Clock Divider Control
CD1 CD0 Osc Cycles per Machine Cycle
0
0
1
1
Switchback Enable
0=Interrupts and serial port activity will not affect
clock divider control bits
1=Enabled Interrupts and serial port activity will
cause a switchback
Power Fail Interrupt Status
0=No power fail interrupt in progress
1=Power fail interrupt in progress
High Priority Interrupt Status
0=No high priority interrupt in progress
1=High priority interrupt in progress
Low Priority Interrupt Status
0=No low priority interrupt in progress
1=Low priority interrupt in progress
Serial Port 1 Transmitter Activity Status
0=Serial port 1 transmitter inactive
1=Serial port 1 transmitter active
Serial Port 1 Receiver Activity Status
0=Serial port 1 receiver inactive
1=Serial port 1 receiver active
Serial Port 0 Transmitter Activity Status
0=Serial port 0 transmitter inactive
1=Serial port 0 transmitter active
Serial Port 0 Receiver Activity Status
0=Serial port 0 receiver inactive
1=Serial port 0 receiver active
0
1
0
1
Reserved
4 (Reset Default)
64 (PMM1)
1024 (PMM2)
98 of 175
High-Speed Microcontroller User’s Guide
RESET
STATE
0,1
0
0
0
0
0
0
0
0
READ/WRITE
ACCESS
Write: 0,1 anytime;
1,0 & 1,1 only when
previously in 0,1
state. Unrestricted
read.
Unrestricted
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
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