DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 53

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

B Register (B)
Real Time Alarm Subsecond Register (RTASS)
Real Time Alarm Second Register (RTAS)
SFR F0h
B.7-0
Bits 7-0
SFR F2h
RTASS.7-0
Bits 7-0
SFR F3h
Bits 7-6
RTAS.5-0
Bits 5-0
RTASS.7
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, * = See description
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, * = See description
RW-*
RW-0
RW-0
B.7
7
7
7
0
B Register. This register serves as a second accumulator for certain arithmetic
operations. It is functionally identical to the B register found in the 80C32.
RTASS.6
Real Time Alarm Subsecond. These bits represent the subsecond alarm which
will be compared against the RTC Subsecond register (RTCSS;FAh). The
ability of a match between the two registers to cause an alarm is controlled by
the RTC Subsecond Register Compare Enable bit (RTCC.7). The contents of
this register will be indeterminate following a no-battery reset, and unchanged
by all other forms of reset.
Reserved. These bits will be 0 when read.
Real Time Alarm Second. These bits represent the second alarm which will be
compared against the RTC Second register (RTCS;FBh). The ability of a match
between the two registers to cause an alarm is controlled by the RTC Second
Register Compare Enable bit (RTCC.6). This register should only be loaded
with values from 0 to 3Bh (0 to 59 seconds). The contents of this register will be
indeterminate following a no-battery reset (except bits 7, 6), and unchanged by
all other forms of reset.
RW-*
RW-0
RW-0
B.6
6
6
6
0
RTASS.5
RTAS.5
RW-*
RW-0
RW-*
B.5
5
5
5
RTASS.4
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RTAS.4
RW-*
RW-0
RW-*
B.4
4
4
4
RTASS.3
RTAS.3
RW-*
RW-0
RW-*
B.3
3
3
3
High-Speed Microcontroller User’s Guide
RTASS.2
RTAS.2
RW-*
RW-0
RW-*
B.2
2
2
2
RTASS.1
RTAS.1
RW-*
RW-0
RW-*
B.1
1
1
1
RTASS.0
RTAS.0
RW-0
RW-*
RW-*
B.0
0
0
0