DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 135

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

The Watchdog Timer is a free running timer. When used as a simple timer with both the reset and
interrupt functions disabled (EWT = 0 and EWDI = 0), the timer will continue to set the Watchdog
Interrupt flag each time the timer completes the selected timer interval as programmed by WD1
(CKCON.7) and WD0 (CKCON.6). Restarting the timer using the RWT (WDCON.0) bit, allows
software to use the timer in a polled time-out mode. The WDIF bit is cleared by software or any reset.
The Watchdog Interrupt is also available for applications that do not need a true Watchdog Reset but
simply a very long timer. The interrupt is enabled using the Enable Watchdog Timer Interrupt (EWDI =
EIE.4) bit. When the time-out occurs, the Watchdog Timer will set the WDIF bit (WDCON.3), and an
interrupt will occur if the global interrupt enable (EA = IE.7) is set. Note that WDIF is set 512 clocks
before a potential Watchdog Reset. The Watchdog Interrupt Flag will indicate the source of the interrupt,
and must be cleared by software.
Using the Watchdog Interrupt during software development can allow the user to select ideal watchdog
reset locations. Code is first developed without enabling the Watchdog Interrupt or Reset functions.
Once the program is complete, the Watchdog Interrupt function is enabled to identify the required
locations in code to set the RWT (WDCON.0) bit. Incrementally adding instructions to reset the
Watchdog Timer prior to each address location (identified by the Watchdog Interrupt) will allow the code
to eventually run without receiving a Watchdog Interrupt. At this point the Watchdog Timer Reset can be
enabled without the potential of generating unwanted resets. At the same time the Watchdog Interrupt
may also be disabled. Proper use of the Watchdog Interrupt with the Watchdog Reset allows interrupt
software to survey the system for errant conditions.
When using the Watchdog Timer as a system monitor, the Watchdog Reset function should be used. If
the Interrupt function were used, the purpose of the watchdog would be defeated. For example, assume
the system is executing errant code prior to the Watchdog Interrupt. The interrupt would temporarily
force the system back into control by vectoring the CPU to the interrupt service routine. Restarting the
Watchdog and exiting by an RETI or RET, would return the processor to the lost position prior to the
interrupt. By using the Watchdog Reset function, the processor is restarted from the beginning of the
program, and therefore placed into a known state.
The Watchdog has four time-out selections based on the input crystal frequency as shown in the figure.
The selections are a preselected number of clocks. Therefore, the actual time-out interval is dependent on
the crystal frequency. Shown below are the four time-outs with some example periods for different
crystal speeds. Note that the time period shown is for the interrupt event. The reset, when enabled, will
occur 512 clocks later regardless of whether the interrupt is used. Therefore the actual Watchdog time-
out period is the number shown below plus 512 clocks. Watchdog generated resets will last for two
machine cycles.
WD1
0
0
1
1
WD0
0
1
0
1
WATCHDOG
INTERVAL
2
2
2
2
17
20
23
26
NUMBER
CLOCKS
67108864
1048576
8388608
131072
OF
1.8432 MHz
36408.88 ms
4551.11 ms
TIME AT
568.89 ms
71.11 ms
135 of 175
11.0592 MHz
6068.15 ms
TIME AT
758.52 ms
11.85 ms
94.81 ms
High-Speed Microcontroller User’s Guide
4194.30 ms
TIME AT
524.29 ms
65.54 ms
16 MHz
8.19 ms
3355.44 ms
TIME AT
419.43 ms
52.43 ms
20 MHz
6.55 ms
2684.35 ms
TIME AT
335.54 ms
41.94 ms
25 MHz
5.24 ms