ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 22

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

ADV7170/ADV7171
The ADV7170/ADV7171 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7170 has 48
subaddresses and the ADV7171 has 26 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allows data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high pe-
riod, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7170/ADV7171 will not issue an acknowledge and will
return to the idle condition. If, in auto-increment mode the user
exceeds the highest subaddress, the following action will be
taken:
1. In Read Mode, the highest subaddress register contents will
2. In Write Mode, the data for the invalid byte will not be
Figure 35 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
SCLOCK
SDATA
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7170/ADV7171 and the part will re-
turn to the idle condition.
START ADDR R/W ACK SUBADDRESS ACK
S
1-7
SEQUENCE
SEQUENCE
Figure 35. Bus Data Transfer
WRITE
READ
8
9
S SLAVE ADDR A(S)
S SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
1-7
8
LSB = 0
9
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
SUB ADDR
SUB ADDR
Figure 36. Write and Read Sequences
1-7
DATA
8
ACK
A(S)
A(S) S SLAVE ADDR A(S)
9
STOP
P
DATA
–22–
LSB = 1
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7170/
ADV7171 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers, in terms of its configuration.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
Figure 37 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 38 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
MR0 BIT DESCRIPTION
Encode Mode Control (MR01–MR00)
These bits are used to set up the encode mode. The ADV7170/
ADV7171 can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M, N) standard video.
Luminance Filter Control (MR02–MR04)
These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Control (MR05–MR07)
These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cutoff frequencies, 0.65 MHz, 1.0 MHz,
1.3 MHz or 2 MHz, along with a choice of CIF or QCIF filters.
A(S)
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
DATA
DATA
A(M)
A(S) P
DATA
A(M)
P
REV. 0