ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 5

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

5 V TIMING SPECIFICATIONS
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND
PIXEL PORT
TELETEXT
RESET CONTROL
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
REV. 0
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.
Temperature range T
TTL input values are 0 to 3 volts, with input rise/fall times
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Pixel Port consists of the following:
Teletext Port consists of the following:
outputs. Analog output load
Pixel Inputs:
Pixel Controls:
Clock Input:
Teletext Output:
Teletext Input:
SCLOCK Frequency
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
Analog Output Delay
DAC Analog Output Skew
f
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t
Digital Output Access Time, t
Data Setup Time, t
Data Hold Time, t
RESET Low Time
CLOCK
3, 4
3, 4, 7
5, 6
MIN
15
HSYNC, FIELD/VSYNC, BLANK
P15–P0
CLOCK
TTXREQ
TTX
4
3, 4
12
18
to T
10
5
11
17
9
3, 5
12
MAX
11
10 pF.
: 0
o
C to +70
14
2
1
13
4
16
3
8
4
7
6
o
C.
Conditions
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
(V
otherwise noted.)
AA
= 4.75 V – 5.25 V
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
1
, V
–5–
REF
= 1.235 V, R
SET
= 150
Min
0
0.6
1.3
0.6
0.6
100
0.6
8
8
3.5
4
4
3
6
. All specifications T
ADV7170/ADV7171
Typ
7
0
27
11
8
48
20
2
6
Max
300
300
16
400
MIN
to T
MAX
Units
kHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
ns
ns
2
s
s
s
s
s
unless